Comtech EF Data CDM-625A - Manual (Page 643)

H–1
Appendix H. EDMAC CHANNEL
H.1 Overview
H.1.1 EDMAC
EDMAC is the acronym for Embedded Distant-end Monitor And Control. This feature permits
user access to the M&C features of modems that are at the distant-end of a satellite link. This is
accomplished by adding extra information to your data, but in a manner that is otherwise
transparent.
On the transmit side:
The data is split into frames – each frame containing 1008 bits (except Rate 21/44 BPSK Turbo,
or when the data rates exceed 2048 kbps, where the frame length is 2928 bits, and Rate 5/16
BPSK Turbo where the frame length is 3072 bits). 48 bits in each frame are overhead, and the
rest of these bits are user data. This increases the rate of transmission by 5% (approximately
1.5% for the Turbo BPSK cases, and for all data rates greater than 2.048 Mbps). For example, if
the user data rate is 64 kbps, the actual transmission rate will now be at 67.2 kbps. Note that
you may also select EDMAC-2 framing, which always uses a 2928 bit frame, and yields a 1.6%
overhead for all modulation types and data rates.
At the start of each frame, a 12-bit synchronization word is added. This allows the demodulator
to find and lock to the start of frame. At regular intervals throughout the frame, additional data
bytes and flag bits are added (a further 36 bits in total). It is these additional bytes that convey
the M&C data.
When framing is used, the normal V.35 scrambler is no longer used. This V.35 approach is called
‘self synchronizing’ because no external information is required in the receiver in order for the
de-scrambling process to recover the original data.
The disadvantage of this method is that it multiplies errors. On average, if one bit error is
present at the input of the descrambler, three output errors are generated. However, there is an
alternative when the data is in a framed format: in this case, a different class of scrambler may
be used – one that uses the start of frame information to start the scrambling process at an
exact known state.
In the receiver, having synchronized to the frame, the de-scrambler can begin its processing at
exactly the right time. This method does not multiply errors, and therefore has a clear
advantage over V.35 scrambling. This is fortunate, as there is a penalty to be paid for adding the