Sundance FC100 v.2.3 - Manual (Page 4)

FC100 - Floating Point Fast Fourier Transform
v2.3
Fast Fourier Transform product manual
October 2005 www.sundance.com - 4 -
Port name Port width Direction Description
clk 1 Input Clock
cke 1 Input Clock enable (active high). Refer to the clock enable section
of this document for more information about this signal.
start 1 Input FFT start signal (active high) and core reset. The signal start
is asserted for one clock cycle to start the core and the
address generators. It is only asserted once for continuous
data processing (the core will restart automatically every time
a transform is complete). A new start pulse will act as a
synchronous reset, will restart the core and discard the
transform that was currently computed.
stop 1 Input FFT stop signal (active high). The signal stop is asserted for
one clock cycle to stop the FFT core. The results of the
current FFT will be discarded once stop has been asserted.
done 1 Output FFT done signal (active high). A done pulse indicates that the
results of the current transform are ready. The done pulse is
active one clock cycle after the last active cycle of the
result_valid signal.
FFTlength 5 input FFT transform length. Please refer to the Transform length
section of this document for more details.
FFT_nIFFT 1 Input FFT direction. High Ù FFT, Low Ù IFFT. This signal is
registered inside the core on a start pulse.
empty_pipeline 1 Input Empty the core pipeline before processing the next FFT/IFFT
pass. If High, this signal will force the core to wait for all the
data of an FFT/IFFT pass to be output before the next pass
can be started. This is useful in a configuration where the
single port processing memory banks are swapped every new
pass. If Low the FFT core will start reading the data from the
memory before the core has completed the calculations from
the previous pass.
This signal is registered inside the core on a start pulse.
tw_din_addr_valid 1 Output Address valid strobe. This signal indicates that the current
addresses on tw_addr and din_addr are valid.
tw_addr Abw Output Twiddle factors address bus. This bus gives the address in the
memory where the twiddle factors must be read from.
din_addr Abw Output Data input address bus. This bus gives the address in the
memory where the input data must be read from.
din_bank 1 Output Data input memory bank. This signal indicates which data
memory bank is used as the input bank.
tw 2.Mbw+2.Ebw
or 64 for
IEEE-754
Input Twiddle factors input. This bus should be connected to the
memory containing the twiddle factors. The data
decomposition is as follows for 2’s complement formats:
Real mantissa: bits Mbw-1 down to 0
Imag mantissa: bits 2.Mbw-1 down to Mbw
Real exponent: bits 2.Mbw+ Ebw-1 down to 2.Mbw
Imag exponent: bits 2.Mbw+ 2.Ebw-1 down to 2.Mbw+ Ebw
IEEE-754:
Real : bits 31 down to 0
Imag : bits 63 down to 32