Sundance SMT356 - Manual (Page 13)

Version 2.1 Page 13 of 26 SMT356356 User Manual
Virtex
The main component which controls the operation of the module is a Virtex FPGA
from Xilinx. This device is volatile in nature, and requires reconfiguring every time the
module is powered on. The configuration data (bitstream) must be presented through
comm port 3.
The bitstream is supplied on the distribution disk as ‘smt356.mcs’. This is an ASCII
text file and a function for configuring is supplied. This function makes use of stdio file
operations.
When this module is used with a TIM with large flash memory, then the configuration
can be stored in this memory and this operation is therefore much faster. Eg. The
SMT332 may be ordered with the 356 configuration in flash memory and a simpler
function is used to configure the Virtex.
When the module is not configured, LED5 will be illuminated. Upon successful
configuration, LED5 will extinguish.
SDB
The sampled data is output on an SDB (Sundance Digital Bus) connector. This is
simple yet versatile bus system, with a protocol for bi-directional data transfer. The
SDB implementation on this module is as an output only.
Once the sample clock is enabled, all ADCs are sampled at the same time at a
frequency selected by Jumper Bank position 1 and/or the divider.
The 14 bit samples occupy the higher 14 bits of the SDB word. Bits 0 and 1 are
undefined.
The sampled data is presented, one channel at a time, to the most significant 14 data
bits of the SDB connector. This data will be transmitted on the SDB as a packet with
the WEN signal active (low) for the whole packet.
The sample data is buffered within a 256 word FIFO.