Sundance SMT376 - Manual (Page 8)

Version 1.7 Page 8 of 24 SMT376 User Manual
TMS320C6211/6711
The processor will run with zero wait states from internal SRAM. The internal memory
is 64k bytes in size and can be partitioned between normal SRAM and/or L2 cache.
An on-board crystal oscillator provides the clock used for the C60 which then
multiplies this by 4 internally.
Boot Mode
The SMT376 is configured to use the following boot sequence each time it is taken
out of reset:
1. The processor copies a bootstrap program from the first part of the flash
memory into internal program RAM starting at address 0.
2. Execution starts at address 0.
The standard bootstrap supplied with the SMT376 then performs the following
operations:
1. All relevant C60 internal registers are set to default values;
2. The FPGA is configured from data held in flash memory and sets up the
communication ports, the global bus and the Sundance Digital/High-speed
Buses. This step must have been completed before data can be sent to the
ComPorts from external sources such as the host or other TIMs;
3. A C4x-style boot loader is executed. This will continually examine the four
communication ports until data appears on one of them. The bootstrap will
then load a program in boot format from that port; the loader will not read data
arriving on other ports. See “Application Development” for details of the boot
loader format;
4. Finally, control is passed to the loaded program.