Sundance SMT376 - Manual (Page 9)

Version 1.7 Page 9 of 24 SMT376 User Manual
The delay between the release of the board reset and the FPGA configuration is
around 0.5s for a SMT376 (150MHz clock).
A typical time to wait after releasing the board reset should be in excess of this delay,
but no damage will result if any of the I/Os are used before they are fully configured.
In fact, the ComPorts will just produce a not ready signal when data is attempted to
be transferred during this time, and then continue normally after the FPGA is
configured.
EMIF Control Registers
The C60 has a single external memory interface (EMIF) which is 32 bits wide.
The C60 contains several registers that control the external memory interface (EMIF).
A full description of these registers can be found in the C60 Peripherals Reference
Guide.
The standard bootstrap will initialise these registers to use the following resources:
Memory space
(EMIF)
Resource Address range
CE0 Spartan 0x80000000 - 0x8FFFFFFF
CE1 Flash 0x90000000 - 0x901FFFFF
CE2 SDRAM bank 0 0xA0000000 - 0xA7FFFFFF
CE3 SDRAM bank 1 0xB0000000 - 0xB7FFFFFF
SDRAM
Memory spaces CE2 & 3 are used to access 256MB of SDRAM over the EMIF.
The speed of the SDRAM is dependant on the processor variant. Using the C6x11,
the SDRAM will operate at 100MHz.
Using the C6713, the SDRAM operates at a programmable rate up to the maximum
allowed on the EMIF (TI data sheet = TBD).
The EMIF CE2 & 3 memory space control registers should be programmed with the
value 0x00000030.