Avago Technologies LSI53C1030 - Manual (Page 87)

LSI53C1030 PCI-X to Dual Channel Ultra320 SCSI Multifunction Controller 4-1
Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
Chapter 4
PCI Host Register
Description
This chapter describes the PCI host register space. This chapter consists
of the following sections:
•
Section 4.1, “PCI Configuration Space Register Description”
•
Section 4.2, “PCI I/O Space and Memory Space Register
Description”
The register map at the beginning of each register description provides
the default bit settings for the register. Shading indicates a reserved bit
or register. Do not access the reserved address areas.
There are two PCI functions on the LSI53C1030. Each PCI function has
its own independent interrupt pin and its own PCI Address space. The
PCI System Address space consists of three regions: Configuration
Space, Memory Space, and I/O Space. PCI Configuration Space
supports the identification, configuration, initialization and error
management functions for the LSI53C1030 PCI devices.
PCI Memory Space [0] and Memory Space [1] form the PCI Memory
Space. PCI Memory Space [0] provides normal system accesses to
memory and PCI Memory Space [1] provides diagnostic memory
accesses. PCI I/O Space provides normal system access to memory.
4.1 PCI Configuration Space Register Description
This section provides bit level descriptions of the PCI Configuration
Space registers.
Table 4.1 defines the PCI Configuration Space registers.
A separate set of PCI Configuration Space registers exists for each PCI
function.
The LSI53C1030 enables, orders, and locates the PCI extended
capability register structures (Power Management, Messaged Signalled