Avago Technologies LSI53C320 - Manual (Page 31)

SCSI Signal Processing 2-13
Version 2.2 Copyright © 2003 by LSI Logic Corporation. All rights reserved.
edge. The duration of the input signal determines the duration of the
output signal.
3. To assure that the LSI53C320 does not sample its own signals, the
LSI53C320 delays sampling until a specified time after the last signal
deassertion.
2.3.5 Request and Acknowledge Signals
The SREQ and SACK signal paths contain controls that guarantee
minimum pulse widths, filter edges, and perform signal retiming.
When performing DT clocking, the LSI53C320 filters both the leading and
trailing signal edges. When performing ST clocking, the LSI53C320 filters
only the leading signal edge. The SREQ and SACK paths are from the
A Side to the B Side and from the B Side to the A Side. The following
steps describe the SREQ and SACK signal processing:
1. The LSI53C320 senses the asserted input signal and forwards it to
the next stage if the direction control permits. The LSI53C320 state
machine develops the direction controls from the sequence of the
bus control signals.
2. The LSI53C320 filters the leading edge of the input and output signal
to ensure that the signal does not switch during the specified hold
time after the leading edge. The duration of the input signal
determines the duration of the output signal after the hold time. The
LSI53C320 guarantees a minimum pulse width.
3. The LSI53C320 passes the signal to the load bus if the signal is not
a data clock. If SREQ or SACK is a data clock, it delays the leading
edge to improve data output setup times. The duration of the input
signal determines the duration of the output signal.
4. The LSI53C320 filters the trailing edge of the signal to prevent signal
bounce after the signal deasserts. The LSI53C320 deasserts the
output signal at the first deasserted edge of the input signal.
5. In the last stage, the LSI53C320 3-states the outputs.
6. To assure that the LSI53C320 does not sample its own signals, the
LSI53C320 delays sampling until a specified time after the last signal
deassertion.