Table 4.3 synchronous clock conversion factor, Synchronous clock conversion factor – Avago Technologies LSI53C825AE User Manual
Page 117
Operating Registers
4-29
Note:
For additional information on how the synchronous transfer
rate is determine, refer to
Chapter 2, “Functional Descrip-
EWS
Enable Wide SCSI
3
When this bit is cleared, all information transfer phases
are assumed to be eight bits, transmitted on SD[7:0]/ and
SDP0/. When this bit is asserted, data transfers are done
16 bits at a time, with the least significant byte on
SD[7:0]/ and SDP0/ and the most significant byte on
SD[15:8]/, SDP1/. Command, Status, and Message
phases are not affected by this bit.
Clearing this bit also clears the Wide SCSI Receive bit in
the
register, which indicates
the presence of a valid data byte in the
register.
CCF[2:0]
Clock Conversion Factor
[2:0]
These bits select a factor by which the frequency of
SCLK is divided before being presented to the SCSI core.
The synchronous portion of the SCSI core can be run at
a different clock rate for Fast SCSI, using the
Synchronous Clock Conversion Factor bits. The bit
encoding is displayed in
. All other combinations
are reserved.
Table 4.3
Synchronous Clock Conversion Factor
SCF2
CCF2
SCF1
CCF1
SCF0
CCF0
Factor
Frequency
SCSI Clock (MHz)
0
0
0
SCLK/3
50.01–75.0
0
0
1
SCLK/1
16.67–25.0
0
1
0
SCLK/1.5
25.01–37.5
0
1
1
SCLK/2
37.51–50.0
1
0
0
SCLK/3
50.01–75.0
1
0
1
Reserved
–
1
1
0
Reserved
–
1
1
1
Reserved
–