Epson 6200A - Manual (Page 79)

Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
MSB LSB
MSB LSB
C –
Z –
D –
I –
C –
Z –
D –
I –
S1C6200/6200A CORE CPU MANUAL EPSON 73
3 INSTRUCTION SET
RET
Return from subroutine
RET
PCSL
←
M(SP), PCSH
←
M(SP+1), PCP
←
M(SP+2), SP
←
SP + 3
1 1 1 1 1 1 0 1 1 1 1 1 FDFH
VI
7
Not affected
Not affected
Not affected
Not affected
Jumps to the return address that was pushed onto the stack when the subroutine
was called.
RET
PCP 1101 0010
PCS 1000 1101 0010 1101
SP BD C0
Memory (SP) 1101 1101
Memory (SP+1) 0010 0010
Memory (SP+2) 0010 0010
RETD e Load immediate data e to memory, and increment X by 2, then return
C –
Z –
D –
I –
RETD e
PCSL
←
M(SP), PCSH
←
M(SP+1), PCP
←
M(SP+2), SP
←
SP + 3,
M(X)
←
e
3
to e
0
, M(X+1)
←
e
7
to e
4
, X
←
X + 2
0 0 0 1 e
7
e
6
e
5
e
4
e
3
e
2
e
1
e
0
100H to 1FFH
I
12
Not affected
Not affected
Not affected
Not affected
Loads 8-bit immediate data e into the data memory location addressed by IX and
executes the RET command. X is incremented by 2.
RETD F5H
PCP 0000 0010
PCS 1010 1011 0010 1101
SP BD C0
Memory (SP) 1101 1101
Memory (SP+1) 0010 0010
Memory (SP+2) 0010 0010
X register 0010 1010 0010 1100
Memory (2AH) 0000 0101
Memory (2BH) 0000 1111
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
MSB LSB