Document Outline

• Revision History
• Imprint
• Disclaimer
• Table of Contents
• List of Tables
  • 1-2 System Relevant Information 1 - 7
  • 1-3 CP384 Main Specifications 1 - 10
  • 1-4 CP384 Digital Input Specifications 1 - 11
  • 1-5 CP384 Digital Output Specifications 1 - 11
  • 1-6 Applied Standards 1 - 13
  • 1-7 Related Publications 1 - 13
  • 2-1 Pinout of the Digital Input and Output Interface Connector CON2 2 - 7
  • 2-2 Pinout of the CPCI Connector CON1 (J1) 2 - 9
  • 2-3 Digital Input Function Modes of the CP384 2 - 10
  • 4-1 Backend Register Address Map 4 - 8
  • 4-2 Input Data Register 4 - 9
  • 4-3 Transparent Input Data Register 4 - 9
  • 4-4 Input Control Register 4 - 9
  • 4-6 Input Event Mask Register 4 - 10
  • 4-5 Programmable Input Sample Rates 4 - 10
  • 4-9 Input Latch-on-Event Register 4 - 11
  • 4-7 Input Event Polarity Register 4 - 11
  • 4-8 Input Status Register 4 - 11
  • 4-10 Input Pattern Mask Register 4 - 12
  • 4-11 Input Pattern Compare Register 4 - 12
  • 4-12 Output Data Register 4 - 12
  • 4-15 Hardware Debug Register 4 - 13
  • 4-16 Hardware Status Register 4 - 13
  • 4-13 Output Control Register 4 - 13
  • 4-14 Output Status Register 4 - 13
  • 4-17 General Interrupt Enable Register 4 - 14
  • 4-18 General Interrupt Pending Register 4 - 14
  • 4-21 ROM Command Register 4 - 15
  • 4-19 Output Status Register 4 - 15
  • 4-20 Input IRQ Register 4 - 15
  • 4-22 ROM Control Register 4 - 16
  • 4-23 Opcodes and Commands 4 - 16
  • 4-24 ROM Status Register 4 - 16
  • 4-25 ROM Data Register 4 - 16
  • 5-1 Debouncing Periods 5 - 4
• List of Figures
  • 1-1 CP384 System Level Interfacing Diagram 1 - 8
  • 1-2 CP384 Front Panel 1 - 9
  • 1-3 CP384 Board (Front View) 1 - 9
  • 2-1 CP384 Board Level Interfacing 2 - 4
  • 2-2 Pin Layout of the Digital Input and Output Interface Connector CON2 2 - 6
  • 2-3 CPCI Connector CON1 (J1) 2 - 8
  • 4-1 Voltage Ranges 4 - 3
  • 4-2 Input Channel Schematic 4 - 4
  • 4-3 Input Configuration (Example for Channel 0) 4 - 4
  • 4-4 Configuration Diagram for All Input Channels 4 - 5
  • 4-5 Digital Output Connectionr 4 - 6
  • 4-6 Digital Output Circuit 4 - 6
  • 4-7 External Reset Connection 4 - 7
• Proprietary Note
• Environmental Protection Statement
• Explanation of Symbols
• For Your Safety
  • High Voltage Safety Instructions
  • Special Handling and Unpacking Instructions
• General Instructions on Usage
• Two Year Warranty
• 1. Introduction
  • 1.1 System Overview
  • 1.2 Product Overview
  • 1.3 Board Overview
    • 1.3.1 Board Introduction
    • 1.3.2 Board Specific Information
  • 1.4 System Relevant Information
    • 1.4.1 System Configuration
    • 1.4.2 Driver Software
  • 1.5 Board Diagrams
    • 1.5.1 System Level Interfacing
    • 1.5.2 Front Panel
    • 1.5.3 Board Layout
  • 1.6 Technical Specifications
  • 1.7 Software Support
  • 1.8 Applied Standards
  • 1.9 Related Publications
• 2. Functional Description
  • 2.1 General Information
  • 2.2 Board Level Interfacing Diagram
  • 2.3 Digital Input Signal Conditioning
  • 2.4 Digital Output Signal Conditioning
  • 2.5 Optoisolation
  • 2.6 DIO ProComm Controller
  • 2.7 System Interfaces
    • 2.7.1 Digital Input and Output Interface
    • 2.7.2 CPCI Interface and Pinout
  • 2.8 CapROM EEPROM
  • 2.9 Monitor and Control (M/C)
  • 2.10 Software
• 3. Installation
  • 3.1 Hardware Installation
    • 3.1.1 Safety Requirements
    • 3.1.2 Installation Procedures
    • 3.1.3 Removal Procedures
  • 3.2 Software Installation
• 4. Configuration
  • 4.1 Jumper Settings
  • 4.2 Digital Input Signal Requirements
    • 4.2.1 Channels
    • 4.2.2 Signal Characteristics
    • 4.2.3 Channel Configuration
  • 4.3 Digital Output Signal Properties
    • 4.3.1 Channels
    • 4.3.2 Connection of External Supply
    • 4.3.3 Channel Connection
  • 4.4 Programming Interface
    • 4.4.1 Access Control Logic (Address Decoder)
    • 4.4.2 Reading Input Data
    • 4.4.3 Debouncing Inputs
    • 4.4.4 Detecting Input Events
    • 4.4.5 Latching on Input Events
    • 4.4.6 Comparing Input Patterns
    • 4.4.7 Writing Output Data
    • 4.4.8 Hardware Debug/Test Registers
    • 4.4.9 Generating Interrupts
    • 4.4.10 Programming the Board Capability ROM
• 5. System Considerations
  • 5.1 Introduction
  • 5.2 General
  • 5.3 Shielding
  • 5.4 Debouncing for Digital Inputs
  • 5.5 Process-Side Signal Conditioning for Digital Inputs
  • 5.6 External Power Supply for Digital Outputs
  • 5.7 Cable Interfacing