Fairchild SEMICONDUCTOR RC5051 - Manual (Page 8)

AN50 APPLICATION NOTE
8
Two MOSFETs in parallel.
We recommend two MOSFETs used in parallel instead of
one single MOSFET. The following significant advantages
are realized using two MOSFETs in parallel:
• Significant reduction of Power dissipation.
Maximum current of 14A with one MOSFET:
P
MOSFET
= (I
2
R
DS,ON
)(Duty Cycle) =
(14) 2 (0.050 * )(3.3+0.4)/(5+0.4-0.35) = 7.2 W
With two MOSFETs in parallel:
P
MOSFET
= (I
2
R
DS,ON
)(Duty Cycle) =
(14/2) 2 (0.037*)(3.3+0.4)/(5+0.4-0.35) = 1.3W/FET
* Note: R
DS,ON
increases with temperature. Assume R
DS,ON
= 25m
Ω
at
25
°
C. R
DS,ON
can easily increase to 50m
Ω
at high temperature when
using a single MOSFET. When using two MOSFETs in parallel, the
temperature effects should not cause the R
DS,ON
to rise above the
listed maximum value of 37m
Ω
.
• Less heat sink required.
With power dissipation down to around one watt and with
MOSFETs mounted flat on the motherboard, considerable
less heat sink is required. The junction-to-case thermal
resistance for the MOSFET package (TO-220) is typically
at 2
°
C/W and the motherboard serves as an excellent heat
sink.
• Higher current capability.
With thermal management under control, this on-board
DC-DC converter is able to deliver load currents up to
14.5A with no performance or reliability concerns.
MOSFET Gate Bias
MOSFET can be biased by one of two methods: Charge
Pump and 12V Gate Bias.
• Method 1. Charge pump (or Boostrap) method.
Figure 5 employs a charge pump to provide gate bias.
Capacitor CP is the charge pump deployed to boost the
voltage of the RC5050 output driver. When the MOSFET
switches off, the source of the MOSFET is at -0.6V.
VCCQP is charged through the Schottky diode to 4.5V.
Thus, the capacitor CP is charged to 5V. When the MOS-
FET turns on, the source of the MOSFET voltage is equal
to 5V. The capacitor voltage follows, and hence provides a
voltage at VCCQP equal to 10V. The Schottky diode is
required to provide the charge path when the MOSFET is
off, and reverses bias when the VCCQP goes to 10V. The
charge pump capacitor, CP, needs to be a high Q, high fre-
quency capacitor. A 1
µ
F ceramic capacitor capacitor is
recommended here.
Figure 5. Charge Pump Configuration
• Method 2. 12V Gate Bias.
Figure 6 illustrates how a 12V source can be used to bias
the VCCQP. A 47
Ω
resistor is used to limit the transient
current into the VCCQP pin and a 1
µ
F capacitor filter is
used to filter the VCCQP supply. This method provides a
higher gate bias voltage (V
GS
) to the MOSFET, and there-
fore reduces the R
DS,ON
of the MOSFET and reduces the
power loss due to the MOSFET. Figure 7 shows how
R
DS,ON
reduces dramatically with V
GS
increases. A 6.2V
Zener diode (D1) is placed to clamp the voltage at VCCQP
to a maximum of 12V and ensure that the absolute maxi-
mum voltage of the IC will not be exceeded
Figure 6. 12V Gate Bias Configuration
Figure 7. R
DS,ON
vs. V
GS
for Selected MOSFETs
PWM/PFM
Control
65-AP50-01
+5V
L1
VCCQP
HIDRV
M1
CP RS
DS1
DS2
CB
VO
PWM/PFM
Control
65-AP50-02
+5V
L1
VCCQP
HIDRV
M1
1 µ F RS
DS1
D1
6.2V
47 Ω
CB
VO
+12V
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.1
1.5 2 2.5 3 3.5 4 5 6 7 8 9 10 11
Gate-Source Voltage, V
GS
(V)
R
DS,ON
(
Ω
)
R(DS)Fuji
R(DS)7060
R(DS)706A
R(DS)-706AEL