FUJITSU MHR2030AT User Manual
Page 167
5.3 Host Commands
C141-E145-02EN
5-93
Table 5.16 DEVICE CONFIGURATION IDENTIFY data structure
Word
Value
Content
0
X'0001'
Data structure revision
1
X'0007'
Multiword DMA modes supported
Bit 15-3: Reserved
Bit 2:
1 = Multiword DMA mode 2 and below are supported
Bit 1:
1 = Multiword DMA mode 1 and below are supported
Bit 0:
1 = Multiword DMA mode 0 is supported
2
X'003F'
Ultra DMA modes supported
Bit 15-6: Reserved
Bit 5:
1 = Ultra DMA mode 5 and below are supported
Bit 4:
1 = Ultra DMA mode 4 and below are supported
Bit 3:
1 = Ultra DMA mode 3 and below are supported
Bit 2:
1 = Ultra DMA mode 2 and below are supported
Bit 1:
1 = Ultra DMA mode 1 and below are supported
Bit 0:
1 = Ultra DMA mode 0 is supported
3-6
-
Maximum LBA address
7
X'00CF'
Command set/feature set supported
Bit 15-9: Reserved
Bit 8:
1 = 48-bit Addressing feature set supported
Bit 7:
1 = Host Protected Area feature set supported
Bit 6:
1 = Automatic acoustic management supported
Bit 5:
1 = READ/WRITE DMA QUEUED commands supported
Bit 4:
1 = Power-up in Standby feature set supported
Bit 3:
1 = Security feature set supported
Bit 2:
1 = SMART error log supported
Bit 1:
1 = SMART self-test supported
Bit 0:
1 = SMART feature set supported
8-254
X'0000'
Reserved
255
X'xxA5'
Integrity word. Bits 15:8 contains the data structure checksum that is
the two's complement of the sum of all byte in words 0 through 254
and the byte consisting of bits 7:0 of word 255.