Mitsubishi Motors DS5000TK - Manual (Page 125)

USER’S GUIDE
050396 124/173
125
INSTRUCTION TIMING
The internal clocking signals are divided to produce the
necessary clock phases, state times, and machine
cycles which define the sequential execution of instruc-
tions. Two clock oscillator periods define one state time.
The first clock oscillator pulse period of a state time is
called the Phase 1 clock. while the second is called the
Phase 2 clock. In general, arithmetic and logical opera-
tions take place during Phase 1 and internal register–
to–register transfers take place during Phase 2.
A machine–cycle is composed of a total of twelve oscil-
lator periods or six state times. The state times within
the machine cycle are numbered S1 through S6. Each
clock oscillator period within the machine cycle is desig-
nated according to the state number and the phase it
represents within the state. Thus, the oscillator periods
are numbered S1P1 (State 1, Phase 1) through S6P2
(State 6, Phase 2).
All of the instruction sequences executed by the CPU
are preceded by a single byte (8–bit) opcode and con-
sist of a total of either one, two, or three bytes. Most of
the instructions execute in one machine cycle. The rest
of the instructions execute in two machine cycles, ex-
cept for multiply (MUL) and divide (DIV) which execute
in four cycles each.
Figure 15–3 is a timing diagram illustrating the memory
access and execution timing for typical instructions
when they are executed from Byte–wide RAM. The tim-
ing shown is referenced to the internally–generated ma-
chine cycles composed of state times and clock oscilla-
tor phases. The relationship between the internal
instruction execution timing and the external signals
XTAL2 and ALE is illustrated in the diagram. Except for
the MOVX instructions, two code bytes from Program
Memory are always read during each machine cycle of
instruction execution. These read operations take place
at state times S1 and S4.
Execution of a 1–byte, 1–cycle instruction is illustrated
in Figure 15–3A. It begins with the opcode byte fetch
which occurs during S1 and the opcode byte is latched
into the Instruction register at S1P2. The code byte
which is read during S4, in this case, is actually the op-
code byte of the next instruction. This byte is effectively
discarded and the Program Counter is not incremented.
Execution of the instruction is completed S6P2, the end
of the machine cycle.
In the 2–byte 1–cycle instruction shown in Figure
15–3B, the opcode is read during S1 while the second
byte of the instruction, or the operand, is read during S4.
Again, execution of the instruction is complete at the
end of S6P2.
A 1–byte, 2–cycle instruction is shown in Figure 15–3C.
In this case the opcode byte is read at S1 of the first ma-
chine cycle. The next opcode is then read three times
during the S1 and S4 of the second machine cycle. The
information is discarded each of these times until it is fi-
nally read when the next instruction is actually
executed.
Finally, Figure 15–3D illustrates the execution of one of
the MOVX instruction which is also a 1–byte, 2–cycle
instruction. However, the execution timing of this unique
in that a Data Memory location is accessed during the
execution of the instruction. This access takes place
during the time period from S4 of the first cycle through
S3 of the second cycle. If the access is made from Data
Memory mapped on the Expanded Bus, then ports P0,
P2, and pins P3.6 and P3.7 will automatically be en-
abled and the read or write operation will take place on
external memory. If the access is made from Data
Memory space which is mapped within the Byte–wide
RAM, then the read or write operation will take place on
the Byte–wide RAM bus and the external port pins will
not be affected.