Document Outline

• 1.0 Introduction
  • 1.1 What You Will Find in This Document
  • 1.2 Related Documents
• 2.0 General Description
  • Figure 1. Block Diagram
  • Figure 2. Internal Architecture
• 3.0 Ball Assignments and Ball List Tables
  • 3.1 Ball Assignments
    • Figure 3. 552-Ball CBGA Assignments (Top View)
  • 3.2 Ball List Tables
    • 3.2.1 Balls Listed in Alphabetic Order by Signal Name
      • Table 1. Ball List in Alphanumeric Order by Signal Name
    • 3.2.2 Balls Listed in Alphabetic Order by Ball Location
      • Table 2. Ball List in Alphanumeric Order by Ball Location
• 4.0 Ball Assignments and Signal Descriptions
  • 4.1 Naming Conventions
    • 4.1.1 Signal Name Conventions
    • 4.1.2 Register Address Conventions
  • 4.2 Interface Signal Groups
    • Figure 4. Interface Signals
  • 4.3 Signal Description Tables
    • Table 3. SPI3 Interface Signal Descriptions (Sheet 1 of 8)
    • Table 4. SerDes Interface Signal Descriptions
    • Table 5. GMII Interface Signal Descriptions (Sheet 1 of 2)
    • Table 6. RGMII Interface Signal Descriptions (Sheet 1 of 2)
    • Table 7. CPU Interface Signal Descriptions (Sheet 1 of 2)
    • Table 8. Transmit Pause Control Interface Signal Descriptions
    • Table 9. Optical Module Interface Signal Descriptions (Sheet 1 of 2)
    • Table 10. MDIO Interface Signal Descriptions
    • Table 11. LED Interface Signal Descriptions
    • Table 12. JTAG Interface Signal Descriptions
    • Table 13. System Interface Signal Descriptions
    • Table 14. Power Supply Signal Descriptions
  • 4.4 Ball Usage Summary
    • Table 15. Ball Usage Summary
  • 4.5 Multiplexed Ball Connections
    • 4.5.1 GMII/RGMII/SerDes/OMI Multiplexed Ball Connections
      • Table 16. Line Side Interface Multiplexed Balls (Sheet 1 of 2)
    • 4.5.2 SPI3 MPHY/SPHY Ball Connections
      • Table 17. SPI3 MPHY/SPHY Interface (Sheet 1 of 3)
  • 4.6 Ball State During Reset
    • Table 18. Definition of Output and Bi-directional Balls During Hardware Reset (Sheet 1 of 2)
  • 4.7 Power Supply Sequencing
    • 4.7.1 Power-Up Sequence
    • 4.7.2 Power-Down Sequence
      • Figure 5. Power Supply Sequencing
      • Table 19. Power Supply Sequencing
  • 4.8 Pull-Up/Pull-Down Ball Guidelines
    • Table 20. Pull-Up/Pull-Down and Unused Ball Guidelines
  • 4.9 Analog Power Filtering
    • Figure 6. Analog Power Supply Filter Network
    • Table 21. Analog Power Balls
• 5.0 Functional Descriptions
  • 5.1 Media Access Controller (MAC)
    • 5.1.1 Features for Fiber and Copper Mode
      • 5.1.1.1 Padding of Undersized Frames on Transmit
      • 5.1.1.2 Automatic CRC Generation
      • 5.1.1.3 Filtering of Receive Packets
        • Table 22. CRC Errored Packets Drop Enable Behavior
      • 5.1.1.4 CRC Error Detection
    • 5.1.2 Flow Control
      • 5.1.2.1 802.3x Flow Control (Full-Duplex Operation)
        • Figure 7. Packet Buffering FIFO
        • Figure 8. Ethernet Frame Format
        • Figure 9. PAUSE Frame Format
        • Table 23. Valid Decodes for TXPAUSEADD[2:0]
        • Figure 10. Transmit Pause Control Interface
    • 5.1.3 Mixed-Mode Operation
      • 5.1.3.1 Configuration
      • 5.1.3.2 Key Configuration Registers
        • Table 24. Operational Mode Configuration Registers
    • 5.1.4 Fiber Mode
      • 5.1.4.1 Fiber Auto-Negotiation
      • 5.1.4.2 Determining If Link Is Established in Auto-Negotiation Mode
      • 5.1.4.3 Fiber Forced Mode
      • 5.1.4.4 Determination of Link Establishment in Forced Mode
    • 5.1.5 Copper Mode
      • 5.1.5.1 Speed
      • 5.1.5.2 Duplex
      • 5.1.5.3 Copper Auto-Negotiation
    • 5.1.6 Jumbo Packet Support
      • 5.1.6.1 Rx Statistics
      • 5.1.6.2 TX Statistics
      • 5.1.6.3 Loss-less Flow Control
    • 5.1.7 Packet Buffer Dimensions
      • 5.1.7.1 TX and RX FIFO Operation
    • 5.1.8 RMON Statistics Support
      • Table 25. RMON Additional Statistics (Sheet 1 of 2)
      • 5.1.8.1 Conventions
      • 5.1.8.2 Advantages
  • 5.2 SPI3 Interface
    • 5.2.1 MPHY Operation
      • 5.2.1.1 SPI3 RX Round Robin Data Transmission
    • 5.2.2 MPHY Logical Timing
      • 5.2.2.1 Transmit Timing
        • Figure 11. MPHY Transmit Logical Timing
      • 5.2.2.2 Receive Timing
        • Figure 12. MPHY Receive Logical Timing
        • Figure 13. MPHY 32-Bit Interface
      • 5.2.2.3 Clock Rates
      • 5.2.2.4 Parity
      • 5.2.2.5 SPHY Mode
      • 5.2.2.6 SPHY Logical Timing
      • 5.2.2.7 Transmit Timing (SPHY)
        • Figure 14. SPHY Transmit Logical Timing
      • 5.2.2.8 Receive Timing (SPHY)
        • Figure 15. SPHY Receive Logical Timing
        • Figure 16. SPHY Connection for Two Intel® IXF1104 MAC Ports (8-Bit Interface)
      • 5.2.2.9 SPI3 Flow Control
    • 5.2.3 Pre-Pending Function
  • 5.3 Gigabit Media Independent Interface (GMII)
    • Figure 17. MAC GMII Interconnect
    • 5.3.1 GMII Signal Multiplexing
    • 5.3.2 GMII Interface Signal Definition
      • Table 26. GMII Interface Signal Definitions
  • 5.4 Reduced Gigabit Media Independent Interface (RGMII)
    • Figure 18. RGMII Interface
    • 5.4.1 Multiplexing of Data and Control
    • 5.4.2 Timing Specifics
    • 5.4.3 TX_ER and RX_ER Coding
      • Table 27. RGMII Signal Definitions
      • Table 28. TX_ER and RX_ER Coding Description
      • Figure 19. TX_CTL Behavior
      • Figure 20. RX_CTL Behavior
      • 5.4.3.1 In-Band Status
    • 5.4.4 10/100 Mbps Functionality
  • 5.5 MDIO Control and Interface
    • 5.5.1 MDIO Address
    • 5.5.2 MDIO Register Descriptions
    • 5.5.3 Clear When Done
    • 5.5.4 MDC Generation
      • 5.5.4.1 MDC High-Frequency Operation
      • 5.5.4.2 MDC Low-Frequency Operation
    • 5.5.5 Management Frames
      • Figure 21. Management Frame Structure (Single-Frame Format)
    • 5.5.6 Single MDI Command Operation
    • 5.5.7 MDI State Machine
      • Figure 22. MDI State
    • 5.5.8 Autoscan Operation
  • 5.6 SerDes Interface
    • 5.6.1 Features
    • 5.6.2 Functional Description
      • 5.6.2.1 Transmitter Operational Overview
      • 5.6.2.2 Transmitter Programmable Driver-Power Levels
        • Table 29. SerDes Driver TX Power Levels
      • 5.6.2.3 Receiver Operational Overview
      • 5.6.2.4 Selective Power-Down
      • 5.6.2.5 Receiver Jitter Tolerance
        • Figure 23. SerDes Receiver Jitter Tolerance
      • 5.6.2.6 Transmit Jitter
      • 5.6.2.7 Receive Jitter
  • 5.7 Optical Module Interface
    • 5.7.1 Intel® IXF1104 MAC-Supported Optical Module Interface Signals
      • Table 30. Intel® IXF1104 MAC-to-SFP Optical Module Interface Connections (Sheet 1 of 2)
    • 5.7.2 Functional Descriptions
      • 5.7.2.1 High-Speed Serial Interface
      • 5.7.2.2 Low-Speed Status Signaling Interface
    • 5.7.3 I·C Module Configuration Interface
      • 5.7.3.1 I2C Control and Data Registers
      • 5.7.3.2 I2C Read Operation
        • Figure 24. I2C Random Read Transaction
      • 5.7.3.3 I2C Write Operation
      • 5.7.3.4 I·C Protocol Specifics
      • 5.7.3.5 Port Protocol Operation
      • 5.7.3.6 Clock and Data Transitions
        • Figure 25. Data Validity Timing
        • Figure 26. Start and Stop Definition Timing
        • Figure 27. Acknowledge Timing
        • Figure 28. Random Read
  • 5.8 LED Interface
    • 5.8.1 Modes of Operation
    • 5.8.2 LED Interface Signal Description
      • Table 31. LED Interface Signal Descriptions
    • 5.8.3 Mode 0: Detailed Operation
      • Figure 29. Mode 0 Timing
      • Table 32. Mode 0 Clock Cycle to Data Bit Relationship
    • 5.8.4 Mode 1: Detailed Operation
      • Figure 30. Mode 1 Timing
      • Table 33. Mode 1 Clock Cycle to Data Bit Relationship
    • 5.8.5 Power-On, Reset, Initialization
    • 5.8.6 LED DATA Decodes
      • Table 34. LED_DATA# Decodes
      • 5.8.6.1 LED Signaling Behavior
        • Table 35. LED Behavior (Fiber Mode)
        • Table 36. LED Behavior (Copper Mode)
  • 5.9 CPU Interface
    • 5.9.1 Functional Description
      • 5.9.1.1 Read Access
        • Figure 31. Read Timing Diagram - Asynchronous Interface
      • 5.9.1.2 Write Access
        • Figure 32. Write Timing Diagram - Asynchronous Interface
      • 5.9.1.3 CPU Timing Parameters
    • 5.9.2 Endian
      • Table 37. Byte Swapper Behavior
  • 5.10 TAP Interface (JTAG)
    • 5.10.1 TAP State Machine
    • 5.10.2 Instruction Register and Supported Instructions
      • Table 38. Instruction Register Description
    • 5.10.3 ID Register
    • 5.10.4 Boundary Scan Register
    • 5.10.5 Bypass Register
  • 5.11 Loopback Modes
    • 5.11.1 SPI3 Interface Loopback
      • Figure 33. SPI3 Interface Loopback Path
    • 5.11.2 Line Side Interface Loopback
      • Figure 34. Line Side Interface Loopback Path
  • 5.12 Clocks
    • 5.12.1 System Interface Reference Clocks
      • 5.12.1.1 CLK125
    • 5.12.2 SPI3 Receive and Transmit Clocks
    • 5.12.3 RGMII Clocks
    • 5.12.4 MDC Clock
    • 5.12.5 JTAG Clock
    • 5.12.6 I2C Clock
    • 5.12.7 LED Clock
• 6.0 Applications
  • 6.1 Change Port Mode Initialization Sequence
  • 6.2 Disable and Enable Port Sequences
    • 6.2.1 Disable Port Sequence
    • 6.2.2 Enable Port Sequence
• 7.0 Electrical Specifications
  • Table 39. Absolute Maximum Ratings
  • Table 40. Recommended Operating Conditions
  • 7.1 DC Specifications
    • Table 41. DC Specifications
    • Table 42. SerDes Transmit Characteristics (Sheet 1 of 2)
    • Table 43. SerDes Receive Characteristics
    • 7.1.1 Undershoot / Overshoot Specifications
      • Table 44. Undershoot / Overshoot Limits
    • 7.1.2 RGMII Electrical Characteristics
      • Table 45. RGMII Power
  • 7.2 SPI3 AC Timing Specifications
    • 7.2.1 Receive Interface Timing
      • Figure 35. SPI3 Receive Interface Timing
      • Table 46. SPI3 Receive Interface Signal Parameters
    • 7.2.2 Transmit Interface Timing
      • Figure 36. SPI3 Transmit Interface Timing
      • Table 47. SPI3 Transmit Interface Signal Parameters
  • 7.3 RGMII AC Timing Specification
    • Figure 37. RGMII Interface Timing
    • Table 48. RGMII Interface Timing Parameters
  • 7.4 GMII AC Timing Specification
    • 7.4.1 1000 Base-T Operation
      • 7.4.1.1 1000 BASE-T Transmit Interface
        • Figure 38. 1000BASE-T Transmit Interface Timing
        • Table 49. GMII 1000BASE-T Transmit Signal Parameters
      • 7.4.1.2 1000BASE-T Receive Interface
        • Figure 39. 1000BASE-T Receive Interface Timing
        • Table 50. GMII 1000BASE-T Receive Signal Parameters
  • 7.5 SerDes AC Timing Specification
    • Figure 40. SerDes Timing Diagram
    • Table 51. SerDes Timing Parameters
  • 7.6 MDIO AC Timing Specification
    • 7.6.1 MDC High-Speed Operation Timing
      • Figure 41. MDC High-Speed Operation Timing
    • 7.6.2 MDC Low-Speed Operation Timing
      • Figure 42. MDC Low-Speed Operation Timing
    • 7.6.3 MDIO AC Timing
      • Figure 43. MDIO Write Timing Diagram
      • Figure 44. MDIO Read Timing Diagram
      • Table 52. MDIO Timing Parameters
  • 7.7 Optical Module and I2C AC Timing Specification
    • 7.7.1 I2C Interface Timing
      • Figure 45. Bus Timing Diagram
      • Figure 46. Write Cycle Diagram
      • Table 53. I2C AC Timing Characteristics (Sheet 1 of 2)
  • 7.8 CPU AC Timing Specification
    • 7.8.1 CPU Interface Read Cycle AC Timing
      • Figure 47. CPU Interface Read Cycle AC Timing
    • 7.8.2 CPU Interface Write Cycle AC Timing
      • Figure 48. CPU Interface Write Cycle AC Timing
      • Table 54. CPU Interface Write Cycle AC Signal Parameters
  • 7.9 Transmit Pause Control AC Timing Specification
    • Figure 49. Pause Control Interface Timing
    • Table 55. Transmit Pause Control Interface Timing Parameters
  • 7.10 JTAG AC Timing Specification
    • Figure 50. JTAG AC Timing
    • Table 56. JTAG AC Timing Parameters
  • 7.11 System AC Timing Specification
    • Figure 51. System Reset AC Timing
    • Table 57. System Reset AC Timing Parameters
  • 7.12 LED AC Timing Specification
    • Figure 52. LED AC Interface Timing
    • Table 58. LED Interface AC Timing Parameters
• 8.0 Register Set
  • 8.1 Document Structure
  • 8.2 Graphical Representation
    • Figure 53. Memory Overview Diagram
  • 8.3 Per Port Registers
    • Figure 54. Register Overview Diagram
  • 8.4 Register Map
    • Table 59. MAC Control Registers ($ Port Index + Offset) (Sheet 1 of 2)
    • Table 60. MAC RX Statistics Registers ($ Port Index + Offset) (Sheet 1 of 2)
    • Table 61. MAC TX Statistics Registers ($ Port Index + Offset)
    • Table 62. PHY Autoscan Registers ($ Port Index + Offset)
    • Table 63. Global Status and Configuration Registers ($ 0x500 - 0X50C)
    • Table 64. RX FIFO Registers ($ 0x580 - 0x5BF) (Sheet 1 of 2)
    • Table 65. TX FIFO Registers ($ 0x600 - 0x63E) (Sheet 1 of 2)
    • Table 66. MDIO Registers ($ 0x680 - 0x683)
    • Table 67. SPI3 Registers ($ 0x700 - 0x716) (Sheet 1 of 2)
    • Table 68. SerDes Registers ($ 0x780 - 0x798)
    • Table 69. Optical Module Registers ($ 0x799 - 0x79F)
    • 8.4.1 MAC Control Registers
      • Table 70. Station Address ($ Port_Index +0x00 - +0x01)
      • Table 71. Desired Duplex ($ Port_Index + 0x02)
      • Table 72. FD FC Type ($ Port_Index + 0x03)
      • Table 73. Collision Distance ($ Port_Index + 0x05)
      • Table 74. Collision Threshold ($ Port_Index + 0x06)
      • Table 75. FC TX Timer Value ($ Port_Index + 0x07)
      • Table 76. FD FC Address ($ Port_Index + 0x08 - + 0x09)
      • Table 77. IPG Receive Time 1 ($ Port_Index + 0x0A)
      • Table 78. IPG Receive Time 2 ($ Port_Index + 0x0B)
      • Table 79. IPG Transmit Time ($ Port_Index + 0x0C)
      • Table 80. Pause Threshold ($ Port_Index + 0x0E)
      • Table 81. Max Frame Size (Addr: Port_Index + 0x0F)
      • Table 82. MAC IF Mode and RGMII Speed ($ Port_Index + 0x10)
      • Table 83. Flush TX ($ Port_Index + 0x11)
      • Table 84. FC Enable ($ Port_Index + 0x12)
      • Table 85. FC Back Pressure Length ($ Port_Index + 0x13)
      • Table 86. Short Runts Threshold ($ Port_Index + 0x14)
      • Table 87. Discard Unknown Control Frame ($ Port_Index + 0x15)
      • Table 88. RX Config Word ($ Port_Index + 0x16) (Sheet 1 of 2)
      • Table 89. TX Config Word ($ Port_Index + 0x17) (Sheet 1 of 2)
      • Table 90. Diverse Config Write ($ Port_Index + 0x18) (Sheet 1 of 2)
      • Table 91. RX Packet Filter Control ($ Port_Index + 0x19) (Sheet 1 of 2)
      • Table 92. Port Multicast Address ($ Port_Index +0x1A - +0x1B)
    • 8.4.2 MAC RX Statistics Register Overview
      • Table 93. MAC RX Statistics ($ Port_Index + 0x20 - + 0x39) (Sheet 1 of 4)
    • 8.4.3 MAC TX Statistics Register Overview
      • Table 94. MAC TX Statistics ($ Port_Index +0x40 - +0x58) (Sheet 1 of 4)
    • 8.4.4 PHY Autoscan Registers
      • Table 95. PHY Control ($ Port Index + 0x60) (Sheet 1 of 2)
      • Table 96. PHY Status ($ Port Index + 0x61) (Sheet 1 of 2)
      • Table 97. PHY Identification 1 ($ Port Index + 0x62)
      • Table 98. PHY Identification 2 ($ Port Index + 0x63)
      • Table 99. Auto-Negotiation Advertisement ($ Port Index + 0x64) (Sheet 1 of 2)
      • Table 100. Auto-Negotiation Link Partner Base Page Ability ($ Port Index + 0x65) (Sheet 1 of 2)
      • Table 101. Auto-Negotiation Expansion ($ Port Index + 0x66) (Sheet 1 of 2)
      • Table 102. Auto-Negotiation Next Page Transmit ($ Port Index + 0x67)
    • 8.4.5 Global Status and Configuration Register Overview
      • Table 103. Port Enable ($0x500)
      • Table 104. Interface Mode ($0x501)
      • Table 105. Link LED Enable ($0x502)
      • Table 106. MAC Soft Reset ($0x505)
      • Table 107. MDIO Soft Reset ($0x506)
      • Table 108. CPU Interface ($0x508)
      • Table 109. LED Control ($0x509)
      • Table 110. LED Flash Rate ($0x50A)
      • Table 111. LED Fault Disable ($0x50B)
      • Table 112. JTAG ID ($0x50C)
    • 8.4.6 RX FIFO Register Overview
      • Table 113. RX FIFO High Watermark Port 0 ($0x580)
      • Table 114. RX FIFO High Watermark Port 1 ($0x581)
      • Table 115. RX FIFO High Watermark Port 2 ($0x582)
      • Table 116. RX FIFO High Watermark Port 3 ($0x583)
      • Table 117. RX FIFO Low Watermark Port 0 ($0x58A)
      • Table 118. RX FIFO Low Watermark Port 1 ($0x58B)
      • Table 119. RX FIFO Low Watermark Port 2 ($0x58C)
      • Table 120. RX FIFO Low Watermark Port 3 ($0x58D)
      • Table 121. RX FIFO Overflow Frame Drop Counter Ports 0 - 3 ($0x594 - 0x597)
      • Table 122. RX FIFO Port Reset ($0x59E)
      • Table 123. RX FIFO Errored Frame Drop Enable ($0x59F) (Sheet 1 of 2)
      • Table 124. RX FIFO Overflow Event ($0x5A0)
      • Table 125. RX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x5A2 - 0x5A5) (Sheet 1 of 2)
      • Table 126. RX FIFO SPI3 Loopback Enable for Ports 0 - 3 ($0x5B2)
      • Table 127. RX FIFO Padding and CRC Strip Enable ($0x5B3)
      • Table 128. RX FIFO Transfer Threshold Port 0 ($0x5B8)
      • Table 129. RX FIFO Transfer Threshold Port 1 ($0x5B9)
      • Table 130. RX FIFO Transfer Threshold Port 2 ($0x5BA)
      • Table 131. RX FIFO Transfer Threshold Port 3 ($0x5BB)
    • 8.4.7 TX FIFO Register Overview
      • Table 132. TX FIFO High Watermark Ports 0 - 3 ($0x600 - 0x603)
      • Table 133. TX FIFO Low Watermark Register Ports 0 - 3 ($0x60A - 0x60D)
      • Table 134. TX FIFO MAC Threshold Register Ports 0 - 3 ($0x614 - 0x617)
      • Table 135. TX FIFO Overflow/Underflow/Out of Sequence Event ($0x61E) (Sheet 1 of 2)
      • Table 136. Loop RX Data to TX FIFO (Line-Side Loopback) Ports 0 - 3 ($0x61F)
      • Table 137. TX FIFO Port Reset ($0x620) (Sheet 1 of 2)
      • Table 138. TX FIFO Overflow Frame Drop Counter Ports 0 - 3 ($0x621 - 0x624)
      • Table 139. TX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x625 - 0x629)
      • Table 140. TX FIFO Occupancy Counter for Ports 0 - 3 ($0x62D - 0x630)
      • Table 141. TX FIFO Port Drop Enable ($0x63D)
    • 8.4.8 MDIO Register Overview
      • Table 142. MDIO Single Command ($0x680)
      • Table 143. MDIO Single Read and Write Data ($0x681)
      • Table 144. Autoscan PHY Address Enable ($0x682)
      • Table 145. MDIO Control ($0x683)
    • 8.4.9 SPI3 Register Overview
      • Table 146. SPI3 Transmit and Global Configuration ($0x700) (Sheet 1 of 3)
      • Table 147. SPI3 Receive Configuration ($0x701) (Sheet 1 of 4)
      • Table 148. Address Parity Error Packet Drop Counter ($0x70A)
    • 8.4.10 SerDes Register Overview
      • Table 149. TX Driver Power Level Ports 0 - 3 ($0x784)
      • Table 150. TX and RX Power-Down ($0x787)
      • Table 151. RX Signal Detect Level Ports 0 - 3 ($0x793)
      • Table 152. Clock and Interface Mode Change Enable Ports 0 - 3 ($0x794)
    • 8.4.11 Optical Module Register Overview
      • Table 153. Optical Module Status Ports 0-3 ($0x799)
      • Table 154. Optical Module Control Ports 0 - 3 ($0x79A)
      • Table 155. I2C Control Ports 0 - 3 ($0x79B)
      • Table 156. I2C Data Ports 0 - 3 ($0x79F)
• 9.0 Mechanical Specifications
  • 9.1 Overview
    • 9.1.1 Features
  • 9.2 Package Specifics
  • 9.3 Package Information
    • 9.3.1 CBGA Package Diagrams
      • Figure 55. CBGA Package Diagram
      • Figure 56. CBGA Package Side View Diagram
    • 9.3.2 Flip Chip-Plastic Ball Grid Array Package Diagram
      • Figure 57. FC-PBGA Package (Top and Bottom Views)
      • Figure 58. FC-PBGA Mechanical Specifications
    • 9.3.3 Top Label Marking Example
      • Figure 59. Package Marking Example
• 10.0 Product Ordering Information
  • Table 157. Product Information
  • Figure 60. Ordering Information - Sample