Intel 8XC196Lx - Manual (Page 36)

8XC196L X SUPPLEMENT
4-2
4.2 INTERRUPT REGISTERS
This section describes the changes in the interrupt register bit definitions for the 8XC196Lx fam-
ily.
Table 4-1. Interrupt Sources, Vectors, and Priorities
Interrupt Source Mnemonic
Interrupt Controller
Service
PTS Service
Name V
ect
o
r
Pr
io
ri
ty
†
Name V
ect
o
r
Pri
o
ri
ty
Nonmaskable Interrupt NMI † INT15 203EH 30 — — —
EXTINT Pin EXTINT INT14 203CH 14 PTS14 205CH 29
Reserved — INT13 203AH 13 PTS13 205AH 28
SIO Receive RI INT12 2038H 12 PTS12 2058H 27
SIO Transmit TI INT11 2036H 11 PTS11 2056H 26
SSIO Channel 1 Transfer SSIO1 INT10 2034H 10 PTS10 2054H 25
SSIO Channel 0 Transfer SSIO0 INT09 2032H 09 PTS09 2052H 24
J1850 Status (LB only) J1850ST INT08 2030H 08 PTS08 2050H 23
Reserved (LA, LD) — INT08 2030H 08 PTS08 2050H 23
Unimplemented Opcode — — 2012H — — — —
Software TRAP Instruction — — 2010H — — — —
J1850 Receive (LB only) J1850RX INT07 200EH 07 PTS07 204EH 22
Reserved (LA, LD) — INT07 200EH 07 PTS07 204EH 22
J1850 Transmit (LB only) J1850TX INT06 200CH 06 PTS06 204CH 21
Reserved (LA, LD) — INT06 200CH 06 PTS06 204CH 21
A/D Conv. Complete (LA, LB) AD_DONE INT05 200AH 05 PTS05 204AH 20
Reserved (LD) — INT05 200AH 05 PTS05 204AH 20
EPA Capture/Compare 0 EPA0 INT04 2008H 04 PTS04 2048H 19
EPA Capture/Compare 1 EPA1 INT03 2006H 03 PTS03 2046H 18
EPA Capture/Compare 2 EPA2 INT02 2004H 02 PTS02 2044H 17
EPA Capture/Compare 3 EPA3 INT01 2002H 01 PTS01 2042H 16
EPA Capture/Compare 6–9,
EPA 0–3, 8–9 Overrun,
EPA Compare 0–1
††† ,
Timer 1 Overflow, &
Timer 2 Overflow
EPA x †† INT00 2000H 00 PTS00 2040H 15
† The NMI pin is not bonded out on the 8XC196L x. To protect against glitches, create a dummy interrupt
service routine that contains a RET instruction.
†† These interrupts are individually prioritized in the EPAIPV register. Read the EPA pending registers
(EPA_PEND and EPA_PEND1) to determine which source caused the interrupt.
††† 87C196LA, LB only. The 83C196LD has no EPA compare-only channels.