Document Outline

• 8XC196Lx Supplement to 8XC196Kx, 8XC196Jx, 87C196CA User’s Manual
  • Copyright Page
  • Contents
  • Figures
    • Figure 21. 8XC196Lx Block Diagram
    • Figure 22. Clock Circuitry (87C196LA, LB Only)
    • Figure 23. Internal Clock Phases (Assumes PLL is ...
    • Figure 24. Effect of Clock Mode on Internal CLKOU...
    • Figure 25. Unerasable PROM 1 (USFR1) Register (LA...
    • Figure 31. Register File Address Map
    • Figure 41. Interrupt Mask (INT_MASK) Register 
    • Figure 42. Interrupt Mask 1 (INT_MASK1) Register ...
    • Figure 43. Interrupt Pending (INT_PEND) Register ...
    • Figure 44. Interrupt Pending 1 (INT_PEND1) Regist...
    • Figure 45. PTS Select (PTSSEL) Register
    • Figure 46. PTS Service (PTSSRV) Register
    • Table 51. Microcontroller Ports 
    • Figure 51. Ports 1, 2, 5, and 6 Internal Structur...
    • Figure 52. Ports 3 and 4 Internal Structure (87C1...
    • Figure 61. SSIO 0 Clock (SSIO0_CLK) Register 
    • Figure 62. SSIO 1 Clock (SSIO1_CLK) Register (Con...
    • Figure 71. EPA Block Diagram (87C196LA, LB Only)
    • Figure 72. EPA Block Diagram (83C196LD Only)
    • Figure 73. EPA Interrupt Mask (EPA_MASK) Register...
    • Figure 74. EPA Interrupt Mask 1 (EPA_MASK1) Regis...
    • Figure 75. EPA Interrupt Pending (EPA_PEND) Regis...
    • Figure 76. EPA Interrupt Pending 1 (EPA_PEND1) Re...
    • Figure 77. EPA Interrupt Priority Vector Register...
    • Figure 81. Integrated J1850 Communications Protoc...
    • Figure 82. J1850 Communications Controller Block ...
    • Figure 83. Huntzicker Symbol Definition for J1850...
    • Figure 84. Typical VPW Waveform
    • Figure 85. Bit Arbitration Example
    • Figure 86. J1850 Message Frames
    • Figure 87. Huntzicker Symbol Definition for the N...
    • Figure 88. Definition for Start and End of Frame ...
    • Figure 89. IFR Type 1 Message Frame
    • Figure 810. IFR Type 2 Message Frame
    • Figure 811. IFR Type 3 Message Frame
    • Figure 812. J1850 Transmitter (J_TX) Register
    • Figure 813. J1850 Transmit Message Structure
    • Figure 814. J1850 Receiver (J_RX) Register
    • Figure 815. J1850 Receive Message Structure
    • Figure 816. J1850 Command (J_CMD) Register 
    • Figure 817. J1850 Configuration (J_CFG) Register ...
    • Figure 818. J1850 Delay (J_DLY) Register
    • Figure 819. J1850 Status (J_STAT) Register (Conti...
    • Figure 91. Reset Source (RSTSRC) Register 
    • Figure 101. Clock Circuitry (87C196LA, LB Only)
    • Figure 111. Slave Programming Circuit
    • Figure 112. Serial Port Programming Circuit
    • Figure A1. 87C196LA 52-pin PLCC Package
    • Figure A2. 87C196LB 52-pin PLCC Package
    • Figure A3. 83C196LD 52-pin PLCC Package
  • Tables
    • Table 11. Related Documents
    • Table 21. Features of the 8XC196Lx and 8XC196Kx P...
    • Table 22. State Times at Various Frequencies
    • Table 23. Relationships Between Input Frequency, ...
    • Table 24. UPROM Programming Values and Locations
    • Table 31. Address Map (Continued)
    • Table 32. Register File Memory Addresses
    • Table 33. 8XC196Lx Peripheral SFRs (Continued)
    • Table 34. Windows (Continued)
    • Table 41. Interrupt Sources, Vectors, and Priorit...
    • Table 71. EPA Channels
    • Table 72. EPA Interrupt Priority Vectors
    • Table 81. J1850 Controller Signals
    • Table 82. Control and Status Registers (Continued...
    • Table 83. Relationships Between Input Frequency, ...
    • Table 84. Huntzicker Symbol Timing Characteristic...
    • Table 111. Signature Word and Programming Voltage...
    • Table 112. 87C196LA, LB OTPROM Address Map 
    • Table 113. Slave Programming Mode Address Map
    • Table 114. Serial Port Programming Mode Address M...
    • Table A1. 87C196LA Signals Arranged by Functional...
    • Table A2. 87C196LB Signals Arranged by Functional...
    • Table A3. 83C196LD Signals Arranged by Functional...
    • Table A4. Definition of Status Symbols 
    • Table A5. 87C196LA, LB Default Signal Conditions ...
    • Table A6. 83C196LD Default Signal Conditions 
• CHAPTER 1 Guide to This Manual
  • 1.1 Manual Contents
  • 1.2 Related Documents
• CHAPTER 2 Architectural Overview
  • 2.1 Microcontroller Features
  • 2.2 Block Diagram
  • 2.3 Internal Timing
  • 2.4 External Timing
  • 2.5 Internal Peripherals
    • 2.5.1 I/O Ports
    • 2.5.2 Synchronous Serial I/O Port
    • 2.5.3 Event Processor Array
    • 2.5.4 J1850 Communications Controller
  • 2.6 Design Considerations
• CHAPTER 3 Address Space
  • 3.1 Address Partitions
  • 3.2 Register File
  • 3.3 Peripheral SPecial-Function Registers
  • 3.4 Windowing
• CHAPTER 4 Standard and PTS Interrupts
  • 4.1 Interrupt Sources, Vectors, and Priorities
  • 4.2 Interrupt Registers
    • 4.2.1 Interrupt Mask Registers
    • 4.2.2 Interrupt Pending Registers
    • 4.2.3 Peripheral Transaction Server Registers
• CHAPTER 5 I/O Ports
  • 5.1 I/O Ports Overview
  • 5.2 Internal Structure for Ports 1, 2, 5, and 6 (B...
    • 5.2.1 Configuring Ports 1, 2, 5, and 6 (Bidirectio...
    • 5.2.2 Special Bidirectional Port Considerations
  • 5.3 Internal Structure for Ports 3 and 4 (Address/...
• CHAPTER 6 Synchronous Serial I/O Port
  • 6.1 SSIO 0 Clock Register
  • 6.2 SSIO 1 Clock Register
• CHAPTER 7 Event Processor Array
  • 7.1 EPA Functional Overview
    • 7.1.1 EPA Mask Registers
    • 7.1.2 EPA Pending Registers
    • 7.1.3 EPA Interrupt Priority Vector Register
• CHAPTER 8 J1850 Communications Controller
  • 8.1 J1850 Functional Overview
  • 8.2 J1850 Controller Signals and Registers
  • 8.3 J1850 Controller Operation
    • 8.3.1 Control State Machine
      • 8.3.1.1 Cyclic Redundancy Check Generator
      • 8.3.1.2 Bus Contention
      • 8.3.1.3 Bit Arbitration
      • 8.3.1.4 Error Detection
    • 8.3.2 Symbol Synchronization and Timing Circuitry
      • 8.3.2.1 Clock Prescaler
      • 8.3.2.2 Digital Filter
      • 8.3.2.3 Delay Compensation
      • 8.3.2.4 Symbol Encoding and Decoding
    • 8.3.3 Bit Arbitration Example
  • 8.4 Message Frames
    • 8.4.1 Standard Messaging
      • 8.4.1.1 Header
      • 8.4.1.2 CRC Byte
      • 8.4.1.3 Normalization Bit
      • 8.4.1.4 Start and End Message Frame Symbols
    • 8.4.2 In-frame Response Messaging
      • 8.4.2.1 IFR Messaging Type 1: Single Byte, Single ...
      • 8.4.2.2 IFR Messaging Type 2: Single Byte, Multipl...
      • 8.4.2.3 IFR Messaging Type 3: Multiple Bytes, Sing...
  • 8.5 Transmitting and Receiving Messages
    • 8.5.1 Transmitting Messages
    • 8.5.2 Receiving Messages
    • 8.5.3 IFR Messages
  • 8.6 Programming the J1850 Controller
    • 8.6.1 Programming the J1850 Command (J_CMD) Regist...
    • 8.6.2 Programming the J1850 Configuration (J_CFG) ...
    • 8.6.3 Programming the J1850 Delay Compensation (J_...
    • 8.6.4 Programming the J1850 Status (J_STAT) Regist...
• CHAPTER 9 Minimum Hardware Considerations
  • 9.1 Identifying the Reset Source
  • 9.2 Design Considerations for 8XC196LA, LB, and LD...
• CHAPTER 10 Special Operating Modes
  • 10.1 Internal Timing
  • 10.2 Entering and Exiting ONCE Mode
• CHAPTER 11 Programming the Nonvolatile Memory
  • 11.1 Signature Word and Programming Voltage Values...
  • 11.2 OTPROM Address Map
  • 11.3 Slave Programming Circuit and Address Map
  • 11.4 Serial Port Programming Circuit and Address M...
• APPENDIX A Signal Descriptions
  • A.1 Functional Groupings of Signals
  • A.2 Default Conditions