2-4 integrated peripherals – Intel ATC6430M User Manual

Page 30

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ATC6430M Mainboard Chapter 3 Award BIOS Setup

27

3-2-4 INTEGRATED PERIPHERALS

This section page includes all the items of

IDE hard drive and Programmed Input/Output features. See also Section “Chipset Features Setup”.

CMOS Setup Utility – Copyright © 1984 – 1998 Award Software

Integrated Peripherals

OnChip Primary PCI IDE Enabled
OnChip Secondary PCI IDE Enabled
IDE Primary Master PIO

Auto

IDE Primary Slave PIO

Auto

IDE Secondary Master PIO Auto
IDE Secondary Slave PIO Auto
IDE Primary Master UDMA Auto
IDE Primary Slave UDMA

Auto

IDE Secondary Master UDMA Auto
IDE Secondary Slave UDMA

Auto

USB Controller

Enabled

USB Keyboard Support Disabled
Init Display First

PCI Slot

AC97 Audio

Auto

AC97 Modem

Auto

IDE HDD Block Mode

Enabled

Power On Function Button Only

xKB Power On Password Enter
xHot Key Power On Ctrl-F1

Onboard FDC Controller

Enabled

Onboard Serial Port 1

3F8/IRQ4

Onboard Serial Port 2

2F8/IRQ3

UART Mode Select Normal

xUART Duplex Mode Half

Onboard Parallel Port 378/IRQ7
Parallel Port Mode

ECP

ECP Mode Use DMA 3
PWRON After PWR-Fail Off
Game Port Address

201

Midi Port Address Disabled

xMidi Port IRQ 7

CIR Port Address Disabled

xCIR Port IRQ 11

Item Help
_____________________
_

Menu Level

Ø

If your IDE hard drive
supports block mode
select Enabled for
automatic detection of
the optimal number of
block read/write per
sector the drive can
support

↑↓←→

Move Enter: Select +/-/PU/PD: Value F10:Save ESC: Exit F1:General Help

F5:Previous Values F6:Fail-safe defaults F7:Optimized Defaults


On-Chip Primary PCI IDE; On-Chip Secondary PCI IDE
This setup item allows you
to either enable or disable the primary/secondary controller. You might choose to disable
the controller if you want to add higher performance or specialized controller.

IDE Primary Master/Slave PIO IDE; Secondary Master/Slave PIO
PIO - Programmed Input/Output, it allows the BIOS to tell the controller what it wants
and then let the controller and the CPU to complete the task by themselves. This is

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