Intel Evaluation Platform Board Manual IQ80960RM - Manual (Page 37)

IQ80960RM/RN Evaluation Board Manual 4-7
i960® RM/RN I/O Processor Overview
Figure 4-5 shows a simplified connection of the Application Accelerator to the i960 RM/RN I/O
Processor Internal Bus.
4.8 Performance Monitor Unit
The Performance Monitoring features aid in measuring and monitoring various system parameters
that contribute to the overall performance of the processor. The monitoring facility is generically
referred to as PMON – Performance Monitoring. The facility is model specific, not architectural;
its intended use is to gather performance measurements that can be used to retune/refine code for
better system level performance.
The PMON facility provided on the i960 RM/RN I/O processor comprises:
• One dedicated global Time Stamp counter, and
• Fourteen (14) Programmable Event counters
The global time stamp counter is a dedicated, free running 32-bit counter.
The programmable event counters are 32-bits wide. Each counter can be programmed to observe
an event from a defined set of events. An event consists of a set of parameters which define a start
condition and a stop condition. The monitored events are selected by programming an event select
register (ESR).
Figure 4-5. Application Accelerator Unit
64-bit
Data Queue
Application Accelerator Unit
Packing/
Unpacking
Unit
80960
Bus Interface Internal Bus
Boolean Unit