Intel IA-32 User Manual
Ia-32 intel, Architecture software developer’s manual, Volume 3a: system programming guide, part 1
Advertising
IA-32 Intel
®
Architecture
Software Developer’s Manual
Volume 3A:
System Programming Guide, Part 1
NOTE: The IA-32 Intel Architecture Software Developer's Manual consists
of five volumes: Basic Architecture, Order Number 253665; Instruction
Set Reference A-M, Order Number 253666; Instruction Set Reference N-Z,
Order Number 253667; System Programming Guide, Part 1, Order
Number 253668; System Programming Guide, Part 2, Order Number
253669. Refer to all five volumes when evaluating your design needs.
Order Number: 253668-019
March 2006
Advertising
Table of contents
Document Outline
- IA-32 Intel® Architecture Software Developer’s Manual
- Disclaimer
- CONTENTS FOR VOLUME 3A AND 3B
- CHAPTER 1 About This Manual
- CHAPTER 2 System Architecture Overview
- 2.1 Overview of the System-Level Architecture
- 2.2 Modes of Operation
- 2.3 System Flags and Fields in the EFLAGS Register
- 2.4 Memory-Management Registers
- 2.5 Control Registers
- 2.6 System Instruction Summary
- 2.6.1 Loading and Storing System Registers
- 2.6.2 Verifying of Access Privileges
- 2.6.3 Loading and Storing Debug Registers
- 2.6.4 Invalidating Caches and TLBs
- 2.6.5 Controlling the Processor
- 2.6.6 Reading Performance-Monitoring and Time-Stamp Counters
- 2.6.7 Reading and Writing Model-Specific Registers
- CHAPTER 3 Protected-Mode Memory Management
- 3.1 Memory Management Overview
- 3.2 Using Segments
- 3.3 Physical Address Space
- 3.4 Logical and Linear Addresses
- 3.5 System Descriptor Types
- 3.6 Paging (Virtual Memory) Overview
- 3.7 Page Translation using 32-Bit Physical Addressing
- 3.8 36-Bit Physical Addressing Using the PAE Paging Mechanism
- 3.8.1 Enhanced Legacy PAE Paging
- 3.8.2 Linear Address Translation With PAE Enabled (4-KByte Pages)
- 3.8.3 Linear Address Translation With PAE Enabled (2-MByte Pages)
- 3.8.4 Accessing the Full Extended Physical Address Space With the Extended Page-Table Structure
- 3.8.5 Page-Directory and Page-Table Entries With Extended Addressing Enabled
- 3.9 36-Bit Physical Addressing Using the PSE-36 Paging Mechanism
- 3.10 PAE-Enabled Paging in IA-32e Mode
- 3.11 Mapping Segments to Pages
- 3.12 Translation Lookaside Buffers (TLBs)
- CHAPTER 4 Protection
- 4.1 Enabling and Disabling Segment and Page Protection
- 4.2 Fields and Flags Used for Segment-Level and Page-Level Protection
- 4.3 Limit Checking
- 4.4 Type Checking
- 4.5 Privilege Levels
- 4.6 Privilege Level Checking When Accessing Data Segments
- 4.7 Privilege Level Checking When Loading the SS Register
- 4.8 Privilege Level Checking When Transferring Program Control Between Code Segments
- 4.8.1 Direct Calls or Jumps to Code Segments
- 4.8.2 Gate Descriptors
- 4.8.3 Call Gates
- 4.8.4 Accessing a Code Segment Through a Call Gate
- 4.8.5 Stack Switching
- 4.8.6 Returning from a Called Procedure
- 4.8.7 Performing Fast Calls to System Procedures with the SYSENTER and SYSEXIT Instructions
- 4.8.8 Fast System Calls in 64-bit Mode
- 4.9 Privileged Instructions
- 4.10 Pointer Validation
- 4.11 Page-Level Protection
- 4.12 Combining Page and Segment Protection
- 4.13 Page-Level Protection and Execute-Disable Bit
- CHAPTER 5 Interrupt and Exception Handling
- 5.1 Interrupt and Exception Overview
- 5.2 Exception and Interrupt Vectors
- 5.3 Sources of Interrupts
- 5.4 Sources of Exceptions
- 5.5 Exception Classifications
- 5.6 Program or Task Restart
- 5.7 NonMaskable Interrupt (NMI)
- 5.8 Enabling and Disabling Interrupts
- 5.9 Priority Among Simultaneous Exceptions and Interrupts
- 5.10 Interrupt Descriptor Table (IDT)
- 5.11 IDT Descriptors
- 5.12 Exception and Interrupt Handling
- 5.13 Error Code
- 5.14 Exception and Interrupt Handling in 64-bit Mode
- 5.15 Exception and Interrupt Reference
- Interrupt 0-Divide Error Exception (#DE)
- Interrupt 1-Debug Exception (#DB)
- Interrupt 2-NMI Interrupt
- Interrupt 3-Breakpoint Exception (#BP)
- Interrupt 4-Overflow Exception (#OF)
- Interrupt 5-BOUND Range Exceeded Exception (#BR)
- Interrupt 6-Invalid Opcode Exception (#UD)
- Interrupt 7-Device Not Available Exception (#NM)
- Interrupt 8-Double Fault Exception (#DF)
- Interrupt 9-Coprocessor Segment Overrun
- Interrupt 10-Invalid TSS Exception (#TS)
- Interrupt 11-Segment Not Present (#NP)
- Interrupt 12-Stack Fault Exception (#SS)
- Interrupt 13-General Protection Exception (#GP)
- Interrupt 14-Page-Fault Exception (#PF)
- Interrupt 16-x87 FPU Floating-Point Error (#MF)
- Interrupt 17-Alignment Check Exception (#AC)
- Interrupt 18-Machine-Check Exception (#MC)
- Interrupt 19-SIMD Floating-Point Exception (#XF)
- Interrupts 32 to 255-User Defined Interrupts
- CHAPTER 6 Task Management
- CHAPTER 7 Multiple-Processor Management
- 7.1 Locked Atomic Operations
- 7.2 Memory Ordering
- 7.3 Propagation of Page Table and Page Directory Entry Changes to Multiple Processors
- 7.4 Serializing Instructions
- 7.5 Multiple-Processor (MP) Initialization
- 7.6 Hyper-Threading and Multi-Core Technology
- 7.7 Detecting Hardware Multi-Threading Support and Topology
- 7.8 Intel® Hyper-Threading Technology Architecture
- 7.8.1 State of the Logical Processors
- 7.8.2 APIC Functionality
- 7.8.3 Memory Type Range Registers (MTRR)
- 7.8.4 Page Attribute Table (PAT)
- 7.8.5 Machine Check Architecture
- 7.8.6 Debug Registers and Extensions
- 7.8.7 Performance Monitoring Counters
- 7.8.8 IA32_MISC_ENABLE MSR
- 7.8.9 Memory Ordering
- 7.8.10 Serializing Instructions
- 7.8.11 MICROCODE UPDATE Resources
- 7.8.12 Self Modifying Code
- 7.8.13 Implementation-Specific HT Technology Facilities
- 7.9 Dual-Core Architecture
- 7.10 Programming Considerations for Hardware Multi-Threading Capable Processors
- 7.11 Management of Idle and Blocked Conditions
- 7.11.1 HLT Instruction
- 7.11.2 PAUSE Instruction
- 7.11.3 Detecting Support MONITOR/MWAIT Instruction
- 7.11.4 MONITOR/MWAIT Instruction
- 7.11.5 Monitor/Mwait Address Range Determination
- 7.11.6 Required Operating System Support
- 7.11.6.1 Use the PAUSE Instruction in Spin-Wait Loops
- 7.11.6.2 Potential Usage of MONITOR/MWAIT in C0 Idle Loops
- 7.11.6.3 Halt Idle Logical Processors
- 7.11.6.4 Potential Usage of MONITOR/MWAIT in C1 Idle Loops
- 7.11.6.5 Guidelines for Scheduling Threads on Logical Processors Sharing Execution Resources
- 7.11.6.6 Eliminate Execution-Based Timing Loops
- 7.11.6.7 Place Locks and Semaphores in Aligned, 128-Byte Blocks of Memory
- CHAPTER 8 Advanced Programmable Interrupt Controller (APIC)
- 8.1 Local and I/O APIC Overview
- 8.2 System Bus Vs. APIC Bus
- 8.3 the Intel® 82489DX External APIC, The APIC, and the xAPIC
- 8.4 Local APIC
- 8.5 Handling Local Interrupts
- 8.6 Issuing Interprocessor Interrupts
- 8.7 System and APIC Bus Arbitration
- 8.8 Handling Interrupts
- 8.8.1 Interrupt Handling with the Pentium 4 and Intel Xeon Processors
- 8.8.2 Interrupt Handling with the P6 Family and Pentium Processors
- 8.8.3 Interrupt, Task, and Processor Priority
- 8.8.4 Interrupt Acceptance for Fixed Interrupts
- 8.8.5 Signaling Interrupt Servicing Completion
- 8.8.6 Task Priority in IA-32e Mode
- 8.9 Spurious Interrupt
- 8.10 APIC Bus Message Passing Mechanism and Protocol (P6 Family, Pentium Processors)
- 8.11 Message Signalled Interrupts
- CHAPTER 9 Processor Management and Initialization
- 9.1 Initialization Overview
- 9.2 x87 FPU Initialization
- 9.3 Cache Enabling
- 9.4 Model-Specific Registers (MSRs)
- 9.5 Memory Type Range Registers (MTRRs)
- 9.6 Initializing SSE/SSE2/SSE3 Extensions
- 9.7 Software Initialization for Real-Address Mode Operation
- 9.8 Software Initialization for Protected-Mode Operation
- 9.9 Mode Switching
- 9.10 Initialization and Mode Switching Example
- 9.11 Microcode Update Facilities
- 9.11.1 Microcode Update
- 9.11.2 Optional Extended Signature Table
- 9.11.3 Processor Identification
- 9.11.4 Platform Identification
- 9.11.5 Microcode Update Checksum
- 9.11.6 Microcode Update Loader
- 9.11.7 Update Signature and Verification
- 9.11.8 Pentium 4, Intel Xeon, and P6 Family Processor Microcode Update Specifications
- 9.11.8.1 Responsibilities of the BIOS
- 9.11.8.2 Responsibilities of the Calling Program
- 9.11.8.3 Microcode Update Functions
- 9.11.8.4 INT 15H-based Interface
- 9.11.8.5 Function 00H-Presence Test
- 9.11.8.6 Function 01H-Write Microcode Update Data
- 9.11.8.7 Function 02H-Microcode Update Control
- 9.11.8.8 Function 03H-Read Microcode Update Data
- 9.11.8.9 Return Codes
- CHAPTER 10 Memory Cache Control
- 10.1 Internal Caches, TLBs, and Buffers
- 10.2 Caching Terminology
- 10.3 Methods of Caching Available
- 10.4 Cache Control Protocol
- 10.5 Cache Control
- 10.6 Self-Modifying Code
- 10.7 Implicit Caching (Pentium 4, Intel Xeon, and P6 Family Processors)
- 10.8 Explicit Caching
- 10.9 Invalidating the Translation Lookaside Buffers (TLBs)
- 10.10 Store Buffer
- 10.11 Memory Type Range Registers (MTRRs)
- 10.11.1 MTRR Feature Identification
- 10.11.2 Setting Memory Ranges with MTRRs
- 10.11.3 Example Base and Mask Calculations
- 10.11.4 Range Size and Alignment Requirement
- 10.11.5 MTRR Initialization
- 10.11.6 Remapping Memory Types
- 10.11.7 MTRR Maintenance Programming Interface
- 10.11.8 MTRR Considerations in MP Systems
- 10.11.9 Large Page Size Considerations
- 10.12 Page Attribute Table (PAT)
- CHAPTER 11 Intel® MMX™ Technology System Programming
- CHAPTER 12 SSE, SSE2 and SSE3 System Programming
- 12.1 Providing Operating System Support for SSE/SSE2/SSE3 Extensions
- 12.1.1 Adding Support to an Operating System for SSE/SSE2/SSE3 Extensions
- 12.1.2 Checking for SSE/SSE2/SSE3 Extension Support
- 12.1.3 Checking for Support for the FXSAVE and FXRSTOR Instructions
- 12.1.4 Initialization of the SSE/SSE2/SSE3 Extensions
- 12.1.5 Providing Non-Numeric Exception Handlers for Exceptions Generated by the SSE/SSE2/SSE3 Instructions
- 12.1.6 Providing an Handler for the SIMD Floating-Point Exception (#XF)
- 12.2 Emulation of SSE/SSE2/SSE3 Extensions
- 12.3 Saving and Restoring the SSE/SSE2/SSE3 State
- 12.4 Saving the SSE/SSE2/SSE3 State on Task or Context Switches
- 12.5 Designing OS Facilities for AUTOMATICALLY Saving x87 FPU, MMX, and SSE/SSE2/SSE3 state on Task or Context Switches
- 12.1 Providing Operating System Support for SSE/SSE2/SSE3 Extensions
- CHAPTER 13 Power and Thermal Management
- 13.1 Enhanced Intel Speedstep® Technology
- 13.2 P-State Hardware Coordination
- 13.3 MWAIT Extensions for Advanced Power Management
- 13.4 Thermal Monitoring and Protection
- CHAPTER 14 Machine-Check Architecture
- 14.1 Machine-Check Exceptions and Architecture
- 14.2 Compatibility with Pentium Processor
- 14.3 Machine-Check MSRs
- 14.4 Machine-Check Availability
- 14.5 Machine-Check Initialization
- 14.6. Interpreting the MCA Error Codes
- 14.7 Guidelines for Writing Machine-Check Software
- CHAPTER 15 8086 Emulation
- 15.1 Real-Address Mode
- 15.2 Virtual-8086 Mode
- 15.3 Interrupt and Exception Handling in Virtual-8086 Mode
- 15.4 Protected-Mode Virtual Interrupts
- CHAPTER 16 Mixing 16-Bit and 32-Bit Code
- CHAPTER 17 IA-32 Architecture Compatibility
- 17.1. IA-32 Processor Families and Categories
- 17.2. Reserved Bits
- 17.3. Enabling New Functions and Modes
- 17.4. Detecting the Presence of New Features Through Software
- 17.5. Intel MMX Technology
- 17.6. Streaming SIMD Extensions (SSE)
- 17.7. Streaming SIMD Extensions 2 (SSE2)
- 17.8. Streaming SIMD Extensions 3 (SSE3)
- 17.9. Hyper-Threading Technology
- 17.10. Dual-Core Technology
- 17.11. Specific Features of Dual-Core Processor
- 17.12. New Instructions In the Pentium and Later IA-32 Processors
- 17.13. Obsolete Instructions
- 17.14. Undefined Opcodes
- 17.15. New Flags in the EFLAGS Register
- 17.16. Stack Operations
- 17.17. x87 FPU
- 17.17.1 Control Register CR0 Flags
- 17.17.2 x87 FPU Status Word
- 17.17.3 x87 FPU Control Word
- 17.17.4 x87 FPU Tag Word
- 17.17.5 Data Types
- 17.17.6 Floating-Point Exceptions
- 17.17.6.1 Denormal Operand Exception (#D)
- 17.17.6.2 Numeric Overflow Exception (#O)
- 17.17.6.3 Numeric Underflow Exception (#U)
- 17.17.6.4 Exception Precedence
- 17.17.6.5 CS and EIP For FPU Exceptions
- 17.17.6.6 FPU Error Signals
- 17.17.6.7 Assertion of the FERR# Pin
- 17.17.6.8 Invalid Operation Exception On Denormals
- 17.17.6.9 Alignment Check Exceptions (#AC)
- 17.17.6.10 Segment Not Present Exception During FLDENV
- 17.17.6.11 Device Not Available Exception (#NM)
- 17.17.6.12 Coprocessor Segment Overrun Exception
- 17.17.6.13 General Protection Exception (#GP)
- 17.17.6.14 Floating-Point Error Exception (#MF)
- 17.17.7 Changes to Floating-Point Instructions
- 17.17.7.1 FDIV, FPREM, and FSQRT Instructions
- 17.17.7.2 FSCALE Instruction
- 17.17.7.3 FPREM1 Instruction
- 17.17.7.4 FPREM Instruction
- 17.17.7.5 FUCOM, FUCOMP, and FUCOMPP Instructions
- 17.17.7.6 FPTAN Instruction
- 17.17.7.7 Stack Overflow
- 17.17.7.8 FSIN, FCOS, and FSINCOS Instructions
- 17.17.7.9 FPATAN Instruction
- 17.17.7.10 F2XM1 Instruction
- 17.17.7.11 FLD Instruction
- 17.17.7.12 FXTRACT Instruction
- 17.17.7.13 Load Constant Instructions
- 17.17.7.14 FSETPM Instruction
- 17.17.7.15 FXAM Instruction
- 17.17.7.16 FSAVE and FSTENV Instructions
- 17.17.8 Transcendental Instructions
- 17.17.9 Obsolete Instructions
- 17.17.10 WAIT/FWAIT Prefix Differences
- 17.17.11 Operands Split Across Segments and/or Pages
- 17.17.12 FPU Instruction Synchronization
- 17.18. Serializing Instructions
- 17.19. FPU and Math Coprocessor Initialization
- 17.20. Control Registers
- 17.21. Memory Management Facilities
- 17.22. Debug Facilities
- 17.23. Recognition of Breakpoints
- 17.24. Exceptions and/or Exception Conditions
- 17.25. Interrupts
- 17.26. Advanced Programmable Interrupt Controller (APIC)
- 17.27. Task Switching and TSs
- 17.28. Cache Management
- 17.29. Paging
- 17.30. Stack Operations
- 17.31. Mixing 16- and 32-Bit Segments
- 17.32. Segment and Address Wraparound
- 17.33. Store Buffers and Memory Ordering
- 17.34. Bus Locking
- 17.35. Bus Hold
- 17.36. Model-Specific Extensions to the IA-32
- 17.37. Two Ways to Run Intel 286 Processor Tasks