Intel IA-32 - Manual (Page 348)

8-24 Vol. 3A
ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)
send a lowest priority IPI is model specific and
should be avoided by BIOS and operating system
software.
010 (SMI) Delivers an SMI interrupt to the target processor
or processors. The vector field must be pro-
grammed to 00H for future compatibility.
011 (Reserved)
100 (NMI) Delivers an NMI interrupt to the target processor
or processors. The vector information is ignored.
101 (INIT) Delivers an INIT request to the target processor or
processors, which causes them to perform an
INIT. As a result of this IPI message, all the target
processors perform an INIT. The vector field must
be programmed to 00H for future compatibility.
101 (INIT Level De-assert)
(Not supported in the Pentium 4 and Intel Xeon
processors.) Sends a synchronization message to
all the local APICs in the system to set their arbi-
tration IDs (stored in their Arb ID registers) to the
values of their APIC IDs (see Section 8.7, “Sys-
tem and APIC Bus Arbitration”). For this delivery
mode, the level flag must be set to 0 and trigger
mode flag to 1. This IPI is sent to all processors,
regardless of the value in the destination field or
the destination shorthand field; however, software
should specify the “all including self” shorthand.
110 (Start-Up) Sends a special “start-up” IPI (called a SIPI) to the
target processor or processors. The vector typical-
ly points to a start-up routine that is part of the
BIOS boot-strap code (see Section 7.5, “Multiple-
Processor (MP) Initialization”). IPIs sent with this
delivery mode are not automatically retried if the
source APIC is unable to deliver it. It is up to the
software to determine if the SIPI was not success-
fully delivered and to reissue the SIPI if necessary.