Intel IA-32 - Manual (Page 555)

Vol. 3A 15-5
8086 EMULATION
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Logical instructions AND, OR, XOR, and NOT.
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Decimal instructions DAA, DAS, AAA, AAS, AAM, and AAD.
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Stack instructions PUSH and POP (to general-purpose registers and segment registers).
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Type conversion instructions CWD, CDQ, CBW, and CWDE.
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Shift and rotate instructions SAL, SHL, SHR, SAR, ROL, ROR, RCL, and RCR.
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TEST instruction.
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Control instructions JMP, Jcc, CALL, RET, LOOP, LOOPE, and LOOPNE.
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Interrupt instructions INT n, INTO, and IRET.
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EFLAGS control instructions STC, CLC, CMC, CLD, STD, LAHF, SAHF, PUSHF, and
POPF.
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I/O instructions IN, INS, OUT, and OUTS.
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Load effective address (LEA) instruction, and translate (XLATB) instruction.
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LOCK prefix.
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Repeat prefixes REP, REPE, REPZ, REPNE, and REPNZ.
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Processor halt (HLT) instruction.
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No operation (NOP) instruction.
The following instructions, added to later IA-32 processors (some in the Intel 286 processor and
the remainder in the Intel386 processor), can be executed in real-address mode, if backwards
compatibility to the Intel 8086 processor is not required.
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Move (MOV) instructions that operate on the control and debug registers.
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Load segment register instructions LSS, LFS, and LGS.
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Generalized multiply instructions and multiply immediate data.
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Shift and rotate by immediate counts.
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Stack instructions PUSHA, PUSHAD, POPA and POPAD, and PUSH immediate data.
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Move with sign extension instructions MOVSX and MOVZX.
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Long-displacement Jcc instructions.
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Exchange instructions CMPXCHG, CMPXCHG8B, and XADD.
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String instructions MOVS, CMPS, SCAS, LODS, and STOS.
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Bit test and bit scan instructions BT, BTS, BTR, BTC, BSF, and BSR; the byte-set-on
condition instruction SETcc; and the byte swap (BSWAP) instruction.
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Double shift instructions SHLD and SHRD.
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EFLAGS control instructions PUSHF and POPF.