3 halt idle logical processors – Intel IA-32 User Manual

Page 319

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Vol. 3A 7-51

MULTIPLE-PROCESSOR MANAGEMENT

The MONITOR and MWAIT instructions may be considered for use in the C0 idle state loops, if
MONITOR and MWAIT are supported.

Example 7-6

An OS Idle Loop with MONITOR/MWAIT in the C0 Idle Loop

// WorkQueue is a memory location indicating there is a thread
// ready to run. A non-zero value for WorkQueue is assumed to
// indicate the presence of work to be scheduled on the processor.
// The following example assumes that the necessary padding has been
// added surrounding WorkQueue to eliminate false wakeups
// The idle loop is entered with interrupts disabled.

WHILE (1) {

IF (WorkQueue) THEN {
// Schedule work at WorkQueue.

} ELSE

{

// No work to do - wait in appropriate C-state handler depending
// on Idle time accumulated.

IF (IdleTime >= IdleTimeThreshhold) THEN {

// Call appropriate C1, C2, C3 state handler, C1
// handler shown below
MONITOR WorkQueue // Setup of eax with WorkQueue

// LinearAddress,

// ECX, EDX = 0

IF (WorkQueue != 0) THEN {

MWAIT

}

}

}

}
// C1 handler uses a Halt instruction.

VOID C1Handler()
{

STI
HLT

}

7.11.6.3

Halt Idle Logical Processors

If one of two logical processors is idle or in a spin-wait loop of long duration, explicitly halt that
processor by means of a HLT instruction.

In an MP system, operating systems can place idle processors into a loop that continuously
checks the run queue for runnable software tasks. Logical processors that execute idle loops
consume a significant amount of core’s execution resources that might otherwise be used by the

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