Intel IA-32 - Manual (Page 114)

3-34 Vol. 3A
PROTECTED-MODE MEMORY MANAGEMENT
3.8.5 Page-Directory and Page-Table Entries With Extended
Addressing Enabled
Figure 3-20 shows the format for the page-directory-pointer-table, page-directory, and
page-table entries when 4-KByte pages and 36-bit extended physical addresses are being
used. Figure 3-21 shows the format for the page-directory-pointer-table and page-directory
entries when 2-MByte pages and 36-bit extended physical addresses are being used. The func-
tions of the flags in these entries are the same as described in Section 3.7.6, “Page-Directory and
Page-Table Entries”. The major differences in these entries are as follows:
•
A page-directory-pointer-table entry is added.
•
The size of the entries are increased from 32 bits to 64 bits.
•
The maximum number of entries in a page directory or page table is 512.
•
The base physical address field in each entry is extended to 24 bits.
NOTE
Older IA-32 processors that implement the PAE mechanism use uncached
accesses when loading page-directory-pointer table entries. This behavior is
model specific and not architectural. More recent IA-32 processors may
cache page-directory-pointer table entries.