Intel IA-32 User Manual
Page 456
10-16 Vol. 3A
MEMORY CACHE CONTROL
10.5.2.1
Selecting Memory Types for Pentium Pro and Pentium II Processors
The Pentium Pro and Pentium II processors do not support the PAT. Here, the effective memory
type for a page is selected with the MTRRs and the PCD and PWT bits in the page-table or page-
directory entry for the page. Table 10-6 describes the mapping of MTRR memory types and
page-level caching attributes to effective memory types, when normal caching is in effect (the
CD and NW flags in control register CR0 are clear). Combinations that appear in gray are imple-
mentation-defined for the Pentium Pro and Pentium II processors. System designers are encour-
aged to avoid these implementation-defined combinations.
When normal caching is in effect, the effective memory type shown in Table 10-6 is determined
using the following rules:
1.
If the PCD and PWT attributes for the page are both 0, then the effective memory type is
identical to the MTRR-defined memory type.
2.
If the PCD flag is set, then the effective memory type is UC.
3.
If the PCD flag is clear and the PWT flag is set, the effective memory type is WT for the
WB memory type and the MTRR-defined memory type for all other memory types.
Table 10-6. Effective Page-Level Memory Type for Pentium Pro and
Pentium II Processors
MTRR Memory Type
1
PCD Value
PWT Value
Effective Memory Type
UC
X
X
UC
WC
0
0
WC
0
1
WC
1
0
WC
1
1
UC
WT
0
X
WT
1
X
UC
WP
0
0
WP
0
1
WP
1
0
WC
1
1
UC
WB
0
0
WB
0
1
WT
1
X
UC
NOTE:
1. These effective memory types also apply to the Pentium 4, Intel Xeon, and Pentium III processors
when the PAT bit is not used (set to 0) in page-table and page-directory entries.