Intel IA-32 - Manual (Page 443)

Vol. 3A 10-3
MEMORY CACHE CONTROL
The IA-32 processors implement four types of caches: the trace cache, the level 1 (L1) cache,
the level 2 (L2) cache, and the level 3 (L3) cache (see Figure 10-1). The uses of these caches
differs from the Pentium 4, Intel Xeon, and P6 family processors, as follows:
•
Pentium 4 and Intel Xeon processors — The trace cache caches decoded instructions
(
μops) from the instruction decoder, and the L1 cache contains only data. The L2 and L3
caches are unified data and instruction caches that are located on the processor chip. (The
L3 cache is only implemented on Intel Xeon processors.)
•
P6 family processors — The L1 cache is divided into two sections: one dedicated to
caching IA-32 architecture instructions (pre-decoded instructions) and one to caching data.
The L2 cache is a unified data and instruction cache that is located on the processor chip.
The P6 family processors do not implement a trace cache.
•
Pentium processors — The L1 cache has the same structure as on the P6 family
processors (and a trace cache is not implemented). The L2 cache is a unified data and
instruction cache that is external to the processor chip on earlier Pentium processors and
implemented on the processor chip in later Pentium processors. For Pentium processors
where the L2 cache is external to the processor, access to the cache is through the system
bus.
The cache lines for the L1 and L2 caches in the Pentium 4 and the L1, L2, and L3 caches in the
Intel Xeon processors are 64 bytes wide. The processor always reads a cache line from system
memory beginning on a 64-byte boundary. (A 64-byte aligned cache line begins at an address
with its 6 least-significant bits clear.) A cache line can be filled from memory with a 8-transfer
burst transaction. The caches do not support partially-filled cache lines, so caching even a single
doubleword requires caching an entire line.
The L1 and L2 cache lines in the P6 family and Pentium processors are 32 bytes wide, with
cache line reads from system memory beginning on a 32-byte boundary (5 least-significant bits
of a memory address clear.) A cache line can be filled from memory with a 4-transfer burst trans-
action. Partially-filled cache lines are not supported.
Store Buffer - Pentium 4 and Intel Xeon processors: 24 entries.
- Pentium M processor: 16 entries.
- P6 family processors: 12 entries.
- Pentium processor: 2 buffers, 1 entry each (Pentium processors with MMX
technology have 4 buffers for 4 entries).
Write Combining
(WC) Buffer - Pentium 4 and Intel Xeon processors: 6 or 8 entries.
- Pentium M processor: 6 entries.
- P6 family processors: 4 entries.
NOTES:
1 Introduced to the IA-32 architecture in the Pentium 4 and Intel Xeon processors.
Table 10-1. Characteristics of the Caches, TLBs, Store Buffer, and
Write Combining Buffer in IA-32 Processors (Contd.)
Cache or Buffer Characteristics