Intel IA-32 - Manual (Page 198)

5-22 Vol. 3A
INTERRUPT AND EXCEPTION HANDLING
5.14 EXCEPTION AND INTERRUPT HANDLING IN 64-BIT MODE
In 64-bit mode, interrupt and exception handling is similar to what has been described for non-
64-bit modes. The following are the exceptions:
•
All interrupt handlers pointed by the IDT are in 64-bit code (this does not apply to the SMI
handler).
•
The size of interrupt-stack pushes is fixed at 64 bits; and the processor uses 8-byte, zero
extended stores.
•
The stack pointer (SS:RSP) is pushed unconditionally on interrupts. In legacy modes, this
push is conditional and based on a change in current privilege level (CPL).
•
The new SS is set to NULL if there is a change in CPL.
•
IRET behavior changes.
•
There is a new interrupt stack-switch mechanism.
•
The alignment of interrupt stack frame is different.
5.14.1 64-Bit Mode IDT
Interrupt and trap gates are 16 bytes in length to provide a 64-bit offset for the instruction pointer
(RIP). The 64-bit RIP referenced by interrupt-gate descriptors allows an interrupt service routine
to be located anywhere in the linear-address space. See Figure 5-7.
Figure 5-7. 64-Bit IDT Gate Descriptors
31 16 15 13 14 12 8 7 0
P Offset 31..16
D
P
L
0 4
31 16 15 0
Segment Selector Offset 15..0 0
TYPE
Interrupt/Trap Gate
DPL
Offset
P
Selector Descriptor Privilege Level
Offset to procedure entry point
Segment Present flag
Segment Selector for destination code segment
4 5
0 0 0
31 0
Offset 63..32 8
31 0
12
11
IST 0 0
2
Reserved
IST Interrupt Stack Table