Intel IA-32 - Manual (Page 29)

Vol. 3A xxix
CONTENTS
PAGE
Figure 11-2. Mapping of MMX Registers to x87 FPU Data Register Stack. . . . . . . . . . . . 11-7
Figure 12-1. Example of Saving the x87 FPU, MMX, SSE, and SSE2 State
During an Operating-System Controlled Task Switch. . . . . . . . . . . . . . . . . . 12-9
Figure 13-1. Processor Modulation Through Stop-Clock Mechanism . . . . . . . . . . . . . . . . 13-2
Figure 13-2. MSR_THERM2_CTL Register for the Pentium M Processor . . . . . . . . . . . . 13-4
Figure 13-3. MSR_THERM2_CTL Register for the Pentium 4 Processor
Supporting TM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
Figure 13-4. IA32_THERM_STATUS MSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
Figure 13-5. IA32_THERM_INTERRUPT MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
Figure 13-6. IA32_CLOCK_MODULATION MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
Figure 14-1. Machine-Check MSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
Figure 14-2. IA32_MCG_CAP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
Figure 14-3. MCG_CAP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
Figure 14-4. IA32_MCG_STATUS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4
Figure 14-5. IA32_MCi_CTL Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5
Figure 14-6. IA32_MCi_STATUS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6
Figure 14-7. IA32_MCi_ADDR MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8
Figure 15-1. Real-Address Mode Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
Figure 15-2. Interrupt Vector Table in Real-Address Mode. . . . . . . . . . . . . . . . . . . . . . . . 15-7
Figure 15-3. Entering and Leaving Virtual-8086 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12
Figure 15-4. Privilege Level 0 Stack After Interrupt or Exception in Virtual-8086
Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-18
Figure 15-5. Software Interrupt Redirection Bit Map in TSS . . . . . . . . . . . . . . . . . . . . . . 15-25
Figure 16-1. Stack after Far 16- and 32-Bit Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6
Figure 17-1. I/O Map Base Address Differences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-32
Figure 18-1. Debug Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3
Figure 18-2. DR6 and DR7 Layout on IA-32 Processors Supporting Intel EM64T . . . . . . 18-7
Figure 18-3. MSR_LASTBRANCH_TOS MSR Layout for the Pentium 4
and Intel Xeon Processor Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-15
Figure 18-4. MSR_DEBUGCTLA MSR for Pentium 4 and Intel Xeon Processors . . . . . 18-16
Figure 18-5. LBR MSR Branch Record Layout for the Pentium 4
and Intel Xeon Processor Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-17
Figure 18-6. MSR_DEBUGCTLB MSR for Pentium M Processors. . . . . . . . . . . . . . . . . 18-24
Figure 18-7. LBR Branch Record Layout for the Pentium M Processor . . . . . . . . . . . . . 18-25
Figure 18-8. DebugCtlMSR Register (P6 Family Processors) . . . . . . . . . . . . . . . . . . . . 18-26
Figure 18-9. Event Selection Control Register (ESCR) for Pentium 4 and
Intel Xeon Processors without HT Technology Support . . . . . . . . . . . . . . . 18-34
Figure 18-10. Performance Counter (Pentium 4 and Intel Xeon Processors) . . . . . . . . . . 18-36
Figure 18-11. Counter Configuration Control Register (CCCR) . . . . . . . . . . . . . . . . . . . . 18-37
Figure 18-12. DS Save Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-41
Figure 18-13. Branch Trace Record Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-42
Figure 18-14. IA-32e Mode DS Save Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-43
Figure 18-15. PEBS Record Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-44
Figure 18-16. Effects of Edge Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-48
Figure 18-17. Event Selection Control Register (ESCR) for the Pentium 4
Processor, Intel Xeon Processor and Intel Xeon Processor MP
Supporting Hyper-Threading Technology . . . . . . . . . . . . . . . . . . . . . . . . . . 18-61
Figure 18-18. Counter Configuration Control Register (CCCR) . . . . . . . . . . . . . . . . . . . . 18-63
Figure 18-19. Block Diagram of 64-bit Intel Xeon Processor MP with 8-MByte L3 . . . . . . 18-66
Figure 18-20. MSR_IFSB_IBUSQx, Addresses: 107CCH and 107CDH. . . . . . . . . . . . . . 18-67
Figure 18-21. MSR_IFSB_ISNPQx, Addresses: 107CEH and 107CFH . . . . . . . . . . . . . . 18-68
Figure 18-22. MSR_IFSB_DRDYx, Addresses: 107D0H and 107D1H. . . . . . . . . . . . . . . 18-69