Intel IA-32 - Manual (Page 106)

3-26 Vol. 3A
PROTECTED-MODE MEMORY MANAGEMENT
3.7.6 Page-Directory and Page-Table Entries
Figure 3-14 shows the format for the page-directory and page-table entries when 4-KByte
pages and 32-bit physical addresses are being used. Figure 3-15 shows the format for the
page-directory entries when 4-MByte pages and 32-bit physical addresses are being used. The
functions of the flags and fields in the entries in Figures 3-14 and 3-15 are as follows:
Page base address, bits 12 through 32
(Page-table entries for 4-KByte pages) — Specifies the physical address of the
first byte of a 4-KByte page. The bits in this field are interpreted as the 20 most-
significant bits of the physical address, which forces pages to be aligned on
4-KByte boundaries.
Figure 3-14. Format of Page-Directory and Page-Table Entries for 4-KByte Pages
and 32-Bit Physical Addresses
31
Available for system programmer’s use
Global page (Ignored)
Page size (0 indicates 4 KBytes)
Reserved (set to 0)
12 11 9 8 7 6 5 4 3 2 1 0
P
S
P
C A 0
Accessed
Cache disabled
Write-through
User/Supervisor
Read/Write
Present
D
P
P
W
T
U
/
S
R
/
W
G Avail Page-Table Base Address
31
Available for system programmer’s use
Global Page
Page Table Attribute Index
Dirty
12 11 9 8 7 6 5 4 3 2 1 0
P
C A D
Accessed
Cache Disabled
Write-Through
User/Supervisor
Read/Write
Present
D
P
P
W
T
U
/
S
R
/
W
Avail Page Base Address
Page-Directory Entry (4-KByte Page Table)
Page-Table Entry (4-KByte Page)
P
A
T G