12 exception and interrupt handling, Figure 5-2, Interrupt and exception handling – Intel IA-32 User Manual
Page 190: Figure 5-2. idt gate descriptors
5-14 Vol. 3A
INTERRUPT AND EXCEPTION HANDLING
5.12
EXCEPTION AND INTERRUPT HANDLING
The processor handles calls to exception- and interrupt-handlers similar to the way it handles
calls with a CALL instruction to a procedure or a task. When responding to an exception or inter-
rupt, the processor uses the exception or interrupt vector as an index to a descriptor in the IDT.
If the index points to an interrupt gate or trap gate, the processor calls the exception or interrupt
handler in a manner similar to a CALL to a call gate (see Section 4.8.2, “Gate Descriptors,”
Figure 5-2. IDT Gate Descriptors
31
16 15
13
14
12
8 7
0
P
Offset 31..16
D
P
L
0
4
31
16 15
0
Segment Selector
Offset 15..0
0
0
1
1
D
Interrupt Gate
DPL
Offset
P
Selector
Descriptor Privilege Level
Offset to procedure entry point
Segment Present flag
Segment Selector for destination code segment
31
16 15
13
14
12
8 7
0
P
D
P
L
0
4
31
16 15
0
TSS Segment Selector
0
1
0
1
0
Task Gate
4
5
0 0 0
31
16 15
13
14
12
8 7
0
P
Offset 31..16
D
P
L
0
4
31
16 15
0
Segment Selector
Offset 15..0
0
1
1
1
D
Trap Gate
4
5
0 0 0
Reserved
Size of gate: 1 = 32 bits; 0 = 16 bits
D