Intel IA-32 - Manual (Page 483)

Vol. 3A 10-43
MEMORY CACHE CONTROL
10.12.3 Selecting a Memory Type from the PAT
To select a memory type for a page from the PAT, a 3-bit index made up of the PAT, PCD, and
PWT bits must be encoded in the page-table or page-directory entry for the page. Table 10-11
shows the possible encodings of the PAT, PCD, and PWT bits and the PAT entry selected with
each encoding. The PAT bit is bit 7 in page-table entries that point to 4-KByte pages (see Figures
3-14 and 3-20) and bit 12 in page-directory entries that point to 2-MByte or 4-MByte pages (see
Figures 3-15, 3-21, and 3-23). The PCD and PWT bits are always bits 4 and 3, respectively, in
page-table and page-directory entries.
The PAT entry selected for a page is used in conjunction with the MTRR setting for the region
of physical memory in which the page is mapped to determine the effective memory type for the
page, as shown in Table 10-7.
10.12.4 Programming the PAT
Table 10-12 shows the default setting for each PAT entry following a power up or reset of the
processor. The setting remain unchanged following a soft reset (INIT reset).
Table 10-11. Selection of PAT Entries with PAT, PCD, and PWT Flags
PAT PCD PWT PAT Entry
0 0 0 PAT0
0 0 1 PAT1
0 1 0 PAT2
0 1 1 PAT3
1 0 0 PAT4
1 0 1 PAT5
1 1 0 PAT6
1 1 1 PAT7
Table 10-12. Memory Type Setting of PAT Entries Following a Power-up or Reset
PAT Entry Memory Type Following Power-up or Reset
PAT0 WB
PAT1 WT
PAT2 UC-
PAT3 UC
PAT4 WB
PAT5 WT
PAT6 UC-
PAT7 UC