Intel IA-32 - Manual (Page 113)

Vol. 3A 3-33
PROTECTED-MODE MEMORY MANAGEMENT
CR4 has no affect on the page size when PAE is enabled.) With the PS flag set, the linear address
is divided into three sections:
•
Page-directory-pointer-table entry—Bits 30 and 31 provide an offset to an entry in the
page-directory-pointer table. The selected entry provides the base physical address of a
page directory.
•
Page-directory entry—Bits 21 through 29 provide an offset to an entry in the page
directory. The selected entry provides the base physical address of a 2-MByte page.
•
Page offset—Bits 0 through 20 provides an offset to a physical address in the page.
3.8.4 Accessing the Full Extended Physical Address Space
With the Extended Page-Table Structure
The page-table structure described in the previous two sections allows up to 4 GBytes of
the 64 GByte extended physical address space to be addressed at one time. Additional 4-GByte
sections of physical memory can be addressed in either of two way:
•
Change the pointer in register CR3 to point to another page-directory-pointer table, which
in turn points to another set of page directories and page tables.
•
Change entries in the page-directory-pointer table to point to other page directories, which
in turn point to other sets of page tables.
Figure 3-19. Linear Address Translation With PAE Enabled (2-MByte Pages)
0
Directory Offset
Page Directory
Directory Entry
2-MByte Page
Physical Address
31 20 21
Linear Address
Page-Directory-
Dir. Pointer Entry
CR3 (PDPTR)
30 29
Pointer Table
Directory
Pointer
4 PDPTE
∗ 512 PDE = 2048 Pages
2
32*
9
21
*32 bits aligned onto a 32-byte boundary
15