Intel IA-32 - Manual (Page 28)

CONTENTS
xxviii Vol. 3A
PAGE
Figure 7-6. Topological Relationships between Hierarchical IDs in a
Hypothetical MP Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-36
Figure 8-1. Relationship of Local APIC and I/O APIC In Single-Processor
Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-3
Figure 8-2. Local APICs and I/O APIC When Intel Xeon Processors Are Used
in Multiple-Processor Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-4
Figure 8-3. Local APICs and I/O APIC When P6 Family Processors Are Used
in Multiple-Processor Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-4
Figure 8-4. Local APIC Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-7
Figure 8-5. IA32_APIC_BASE MSR (APIC_BASE_MSR in P6 Family) . . . . . . . . . . . . . . 8-11
Figure 8-6. Local APIC ID Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12
Figure 8-7. Local APIC Version Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15
Figure 8-8. Local Vector Table (LVT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-16
Figure 8-9. Error Status Register (ESR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20
Figure 8-10. Divide Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21
Figure 8-11. Initial Count and Current Count Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21
Figure 8-12. Interrupt Command Register (ICR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-23
Figure 8-13. Logical Destination Register (LDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29
Figure 8-14. Destination Format Register (DFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29
Figure 8-15. Arbitration Priority Register (APR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-31
Figure 8-16. Interrupt Acceptance Flow Chart for the Local APIC (Pentium 4 and
Intel Xeon Processors) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-33
Figure 8-17. Interrupt Acceptance Flow Chart for the Local APIC (P6 Family and
Pentium Processors) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-35
Figure 8-18. Task Priority Register (TPR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-37
Figure 8-19. Processor Priority Register (PPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-38
Figure 8-20. IRR, ISR and TMR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-39
Figure 8-21. EOI Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-40
Figure 8-22. CR8 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-41
Figure 8-23. Spurious-Interrupt Vector Register (SVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-42
Figure 8-24. Layout of the MSI Message Address Register . . . . . . . . . . . . . . . . . . . . . . . . 8-44
Figure 8-25. Layout of the MSI Message Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-45
Figure 9-1. Contents of CR0 Register after Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-5
Figure 9-2. Version Information in the EDX Register after Reset . . . . . . . . . . . . . . . . . . . .9-5
Figure 9-3. Processor State After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21
Figure 9-4. Constructing Temporary GDT and Switching to Protected Mode
(Lines 162-172 of List File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-30
Figure 9-5. Moving the GDT, IDT, and TSS from ROM to RAM (Lines 196-261
of List File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-31
Figure 9-6. Task Switching (Lines 282-296 of List File) . . . . . . . . . . . . . . . . . . . . . . . . . .9-32
Figure 9-7. Applying Microcode Updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-36
Figure 9-8. Microcode Update Write Operation Flow [1]. . . . . . . . . . . . . . . . . . . . . . . . . . 9-59
Figure 9-9. Microcode Update Write Operation Flow [2]. . . . . . . . . . . . . . . . . . . . . . . . . . 9-60
Figure 10-1. Cache Structure of the Pentium 4 and Intel Xeon Processors . . . . . . . . . . . . 10-1
Figure 10-2. Cache-Control Registers and Bits Available in IA-32 Processors . . . . . . . .10-12
Figure 10-3. Mapping Physical Memory With MTRRs . . . . . . . . . . . . . . . . . . . . . . . . . . .10-26
Figure 10-4. IA32_MTRRCAP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-27
Figure 10-5. IA32_MTRR_DEF_TYPE MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-28
Figure 10-6. IA32_MTRR_PHYSBASEn and IA32_MTRR_PHYSMASKn
Variable-Range Register Pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-31
Figure 10-7. IA32_CR_PAT MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-42
Figure 11-1. Mapping of MMX Registers to Floating-Point Registers . . . . . . . . . . . . . . . . . 11-2