Intel IA-32 - Manual (Page 528)

14-2 Vol. 3A
MACHINE-CHECK ARCHITECTURE
14.3 MACHINE-CHECK MSRS
Machine check MSRs in the Pentium 4, Intel Xeon, and P6 family processors consist of a set of
global control and status registers and several error-reporting register banks (see Figure 14-1).
Each error-reporting bank is associated with a specific hardware unit (or group of hardware
units) in the processor. Use RDMSR and WRMSR to read and to write these registers.
14.3.1 Machine-Check Global Control MSRs
The machine-check global control MSRs include the IA32_MCG_CAP, IA32_MCG_STATUS,
and IA32_MCG_CTL. See Appendix B, “Model-Specific Registers (MSRs),” for the addresses
of these registers.
The structure of the IA32_MCG_CAP is implemented differently in Pentium 4 and Intel Xeon
processors and in P6 family processors. Also, note that the register names used for P6 family
processors do not have the ‘IA32’ prefix.
14.3.1.1 IA32_MCG_CAP MSR (Pentium 4 and Intel Xeon Processors)
The IA32_MCG_CAP MSR is a read-only register that provides information about the
machine-check architecture implementation in Pentium 4 and Intel Xeon processors (see
Figure 14-2).
Figure 14-1. Machine-Check MSRs
0
63 0
63
IA32_MCG_CAP MSR
IA32_MCG_STATUS MSR
Error-Reporting Bank Registers
0
63 0
63
IA32_MCi_CTL MSR
IA32_MCi_STATUS MSR
0
63 0
63
IA32_MCi_ADDR MSR
IA32_MCi_MISC MSR
Global Control MSRs
(One Set for Each Hardware Unit)
0 63
IA32_MCG_CTL MSR