Sony MDX-61 User Manual
Page 24
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Pin No.
Pin Name
I/O
Function
50
VSS
–
Ground terminal
51
VDD
–
Power supply terminal (+3.3V)
52-55
A03-A00
O
Address signal output to the RAM (IC501)
56-60
A04-A08
O
Address signal output to the RAM (IC501)
61
XOE
O
Output enable control signal output to the RAM (IC501)
62
XCAS
O
Column address strobe signal output to the RAM (IC501)
63
VSS
–
Ground terminal
64
XCS
O
Chip select signal output Not used this set (OPEN)
65
A09
O
Address signal output to the RAM (IC501)
66
XRAS
O
Row address strobe signal output to the RAM (IC501)
67
XWE
O
Reading/Writing control signal output to the RAM (IC501)
68,69
D1,D0
I/O
RAM (IC501) data bus
70,71
D2,D3
I/O
RAM (IC501) data bus
72-74
D4-D6
I/O
Data bus Not used this set (OPEN)
75
VSS
–
Ground terminal
76
D7
I/O
Data bus Not used this set (OPEN)
77
ERR
I/O
Input /output terminal of the error (C2PO) data signal to the external RAM
Not used this set (OPEN)
78
EXTC2R
I
External RAM selection signal input for the error data writing (When “H” : External RAM)
(Fixed at “L”)
79
BUSY
O
BUSY signal output of the RAM access Not used this set (OPEN)
80
EMP
O
Empty or before the full of the ATRAC data (When DSC=ASC+1 : “H”)
Not used this set (OPEN)
81
FUL
O
Full or before the empty of the ATRAC data (When ASC=DSC+1 : “H”)
Not used this set (OPEN)
82
EQL
O
Empty of the ATRAC data (When DSC=ASC : “H”)
83
MDLK
O
Indicate the main/sub of the recording or playback data (When sub and linking : “H”,
When the main : “L”)
Not used this set (OPEN)
84
CPSY
O
Interpolation sync signal output Not used this set (OPEN)
85
CTMD0
O
DSC (Difference Signal Control) counter mode output
Not used this set (OPEN)
86
CTMD1
O
DSC (Difference Signal Control) counter mode output
Not used this set (OPEN)
87
SPO
O
System clock (512Fs=22.5792MHz) signal output to CXD2535CR (IC200) and D/A converter (IC550)
88
VSS
–
Ground terminal
89
MDSY
O
Sync detection signal output of the main data Not used this set (OPEN)
90
LRCK
I
L/R clock (44.1kHz) signal input from CXD2535CR (IC200)
91
BCK
I
Bit clock (2.8224MHz) signal input from CXD2535CR (IC200)
92
C2PO
I
C2PO (indicate the error mode of the data) signal input from CXD2535BR (IC200)
When playback : C2PO (“H”), When digital recording : D. IN-Vflag, When analog recording : “L”
93
DATA
I/O
When recording : Record audio data signal output (Not used this set)
When playback : Playback audio data signal input from CXD2535CR (IC200)
94
DIDT
I
16-bit data input terminal for the digital audio in Not used this set (Fixed at “L”)
95
DODT
O
16-bit data output terminal for the digital audio out Not used this set (OPEN)
96
DIRCPB
O
Disc drive, Record or playback mode output of the EFM encoder/decoder Not used this set (OPEN)
97
MIN
I
Defect ON/OFF selection signal input from CXD2535CR (IC200)
98
SPOSL
I
IN/OUT selection input terminal of the pin *¶ (“L” : IN, “H” : OUT) (Fixed at “H”)
99
MCK
O
Internal master clock signal output terminal of the RAM controller
100
VSS
–
Ground terminal