Tk-2160, Circuit description, Transmitter system – Kenwood TK-2160 User Manual

Page 9: Fig. 6 pll circuit 3) unlock detector, Fig. 7 unlock detector circuit, 1) microphone amplifier, 4) encode signalling, 2) drive and final amplifier

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TK-2160

9

CIRCUIT DESCRIPTION

PLL DATA

X1

16.8MHz

REF OSC

1M

1N

PLL IC IC1

PHASE

COMPARATOR

CHARGE

PUMP

LPF

5kHz/6.25kHz

D3, 5, 7, 8

D4, 6, 9, 10

Q6

TX VCO

Q5

RX VCO

Q9

BUFF AMP

Q11

RF AMP

Q7

DOUBLER

Q8, 12

T/R SW

5kHz/6.25kHz

LPF

RX

TX

Fig. 6 PLL circuit

3) Unlock Detector

If a pulse signal appears at the LD pin of IC1, an unlock
condition occurs, and the DC voltage obtained from C19,R6
and Q1 causes the voltage applied to the microprocessor
to go high. When the microprocessor detects this condition,
the transmitter is disabled, ignoring the push-to-talk switch
input signal. (See Fig. 7)

Fig. 7 Unlock detector circuit

5C

R6

Q1

C19

R7

IC805

IC1

LD

UL

PLL IC

CPU

R16

4. Transmitter System

1) Microphone Amplifier

The signal from the microphone passes through the IC601.
When encoding DTMF, it is turned OFF for muting the
microphone input signal by IC601.
The signal passes through the Audio processor (IC601) for
the maximum deviation adjustment, and goes to the VCXO
modulation input.

Fig. 8 Microphone amplifier

Fig. 9 Drive and final amplifier and APC circuit

3) APC Circuit

The APC circuit always monitors the current flowing through
the RF power amplifier (Q211) and keeps a constant current.
The voltage drop at R264, R265 and R270 is caused by the
current flowing through the RF power amplifier and this
voltage is applied to the differential amplifier IC201(1/2).
IC201(2/2) compares the output voltage of IC201(1/2) with
the reference voltage from IC805. The output of IC201(2/2)
controls the VG of the RF power amplifier, drive amplifier
and pre-drive amplifier to make both voltages the same.
The change of power high/low is carried out by the change
of the reference voltage.

4) Encode Signalling

(1) QT/DQT
QT,DQT data of the LSDTCXO Line is output from pin 22 of
the CPU. The signal passes through a low-pass CR filter
and goes to the TCXO(X1).
The QT,DQT data of the LSDVCO Line is output from pin

2) Drive and Final Amplifier

The signal from the T/R switch (D201 is on) is amplified by
the drive amplifier (Q207) to 50mW.
The output of the drive amplifier is amplified by the RF power
amplifier (Q211) to 5.0W (1W when the power is low). The
RF power amplifier consists of two MOS FET stages. The
output of the RF power amplifier is then passed through
the harmonic filter (LPF) and antenna switch (D204 and
D206) and applied to the antenna terminal.

From

T/R SW

(D201)

DRIVE

AMP

RF

POWER AMP

LPF

ANT

SW

D204
D206

ANT

VG

VG

Q207

Q211

Pre-DRIVE

AMP

Q206

VDD

VG

R264

R265

R270

+B

IC201

(2/2)

IC201

(1/2)

PCTV

(IC805)

IC601

IC805

LPF

DTMF/2 TONE

LSDTCXO

LSDVCO

CPU

AGC

VCO

MIC

X1

TCXO

LPF

IC606

BUFFER

LPF

AQUA

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