8 stereo decoder, Digital interface (3-wire bus), Tea5880ts – Philips TEA5880TS User Manual
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© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data sheet
Rev. 02 — 26 April 2004
8 of 27
Philips Semiconductors
TEA5880TS
Integrated FM stereo radio IC for host processor tuning
7.8 Stereo decoder
The PLL stereo decoder is adjustment free. The stereo decoder can be switched to mono
via the digital interface.
8.
Digital interface (3-wire bus)
The TEA5880TS has a 3-wire bus with read/write, clock and data line.
The register set of the TEA5880TS can be accessed via the digital interface.
The pins given in
are defined for the digital interface of the TEA5880TS.
Table 4:
Digital interface pins
Pin number
Name
Type
Description
Remark
Pin 6
R/W
input
LOW is read from TEA5880TS;
HIGH is write to TEA5880TS
Pin 8
CLOCK
input
clock
rising edge
Pin 7
DATA
input/output
bidirectional data
Fig 4.
Digital interface block diagram.
001aaa668
OUTPUT
SOURCE
SELECTOR
CONTROL
REGISTER A
ADDRESS
DECODER
CONTROL
REGISTER B
CONTROL
REGISTER C
REST OF THE
REGISTERS
STATUS REGISTER
15 BITS SIPO (SERIAL IN PARALLEL OUT)
stereo LED
stereo clock
IF OSC
R/W
FM OSC
CLOCK
DATA
COUNTER 1 (16 bits)
16 BITS PISO (PARALLEL IN SERIAL OUT)
R/W
11 bits data
4 bits data
16 bits data
16 bits data
CLOCK
R/W
R/W
enable
counter 1
control bits
control bits
control bits
control bits
1-bit data