NEC VR4133 - Manual (Page 4)

Operating Precautions for V R 4133 TM
(A) Table of Operating Precautions
µPD30133
Rev.
1.1 1.2 1.3 1.4 1.5 No. Outline
Rank Note I,K E P X L
1
Simultaneous locking of cache lines with
the same index
    
2
Reception of non IEEE802.3 conformant
packages
    
3 Register content in Ether0/1 blocks     
4 Read access from external PCI master     
5 Write access to external I/O area     
6
Branch delay slot of JAL(X) instruction in
MIPS16 mode
    
7 Disconnect at the end of PCI burst cycle     
8 Ethernet: receive short packet     
9
Ethernet: excessive data transfer into
memory
    
10 Ethernet: transmit short packet     
11
Usage PCI and Ether/CEU/BCU/CSI (using
DMA mode) simultaneously
    
12 Bus arbitration of Internal Bus Arbiter     
13 XX-Bit of CP0 status register     
14 PCI DMA function     
 : Not applicable
 : applicable
Note: The rank is indicated by the letter appearing at the 5
th position from the left in the lot number,
marked on each product.
4 Customer Notification