NEC Network Controller uPD98502 User Manual
NEC Hardware
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Table of contents
Document Outline
- COVER
- PREFACE
- CHAPTER 1 INTRODUCTION
- 1.1 Features
- 1.2 Ordering Information
- 1.3 System Configuration
- 1.4 Block Diagram (Summary)
- 1.5 Block Diagram (Detail)
- 1.6 Pin Configuration (Bottom View)
- 1.7 Pin Function
- 1.7.1 Power supply
- 1.7.2 System PLL power supply
- 1.7.3 USB PLL power supply
- 1.7.4 System control interface
- 1.7.5 Memory interface
- 1.7.6 PCI interface
- 1.7.7 ATM interface
- 1.7.8 Ethernet interface
- 1.7.9 USB interface
- 1.7.10 UART interface
- 1.7.11 Micro Wire interface
- 1.7.12 Parallel port interface
- 1.7.13 Boundary scan interface
- 1.7.14 I.C. – open
- 1.7.15 I.C.– pull down
- 1.7.16 I.C. – pull down with resistor
- 1.7.17 I.C. – pull up
- 1.8 I/O Register Map
- 1.9 Memory Map
- 1.10 Reset Configuration
- 1.11 Interrupts
- 1.12 Clock Control Unit
- CHAPTER 2 VR4120A
- 2.1 Overview for VR4120A
- 2.1.1 Internal block configuration
- 2.1.2 VR4120A registers
- 2.1.3 VR4120A instruction set overview
- 2.1.4 Data formats and addressing
- 2.1.5 Coprocessors (CP0)
- 2.1.6 Floating-point unit (FPU)
- 2.1.7 CPU core memory management system (MMU)
- 2.1.8 Translation lookaside buffer (TLB)
- 2.1.9 Operating modes
- 2.1.10 Cache
- 2.1.11 Instruction Pipeline
- 2.2 MIPS III Instruction Set Summary
- 2.3 Pipeline
- 2.4 Memory Management System
- 2.5 Exception Processing
- 2.6 Initialization Interface
- 2.7 Cache Memory
- 2.8 CPU Core Interrupts
- 2.1 Overview for VR4120A
- CHAPTER 3 SYSTEM CONTROLLER
- 3.1 Overview
- 3.2 Registers
- 3.2.1 Register map
- 3.2.2 S_GMR (General Mode Register)
- 3.2.3 S_GSR (General Status Register)
- 3.2.4 S_ISR (Interrupt Status Register)
- 3.2.5 S_IMR (Interrupt Mask Register)
- 3.2.6 S_NSR (NMI Status Register)
- 3.2.7 S_NER (NMI Enable Register)
- 3.2.8 S_VER (Version Register)
- 3.2.9 S_IOR (IO Port Register)
- 3.2.10 S_WRCR (Warm Reset Control Register)
- 3.2.11 S_WRSR (Warm Reset Status Register)
- 3.2.12 S_PWCR (Power Control Register)
- 3.2.13 S_PWSR (Power Status Register)
- 3.3 CPU Interface
- 3.4 Memory Interface
- 3.4.1 Overview
- 3.4.2 Memory regions
- 3.4.3 Memory signal connections
- 3.4.4 Memory performance
- 3.4.5 RMMDR (ROM Mode Register)
- 3.4.6 RMATR (ROM Access Timing Register)
- 3.4.7 SDMDR (SDRAM Mode Register)
- 3.4.8 SDTSR (SDRAM Type Selection Register)
- 3.4.9 SDPTR (SDRAM Precharge Timing Register)
- 3.4.10 SDRMR (SDRAM Refresh Mode Register)
- 3.4.11 SDRCR (SDRAM Refresh Timer Count Register)
- 3.4.12 MBCR (Memory Bus Control Register)
- 3.4.13 Boot ROM
- 3.4.14 SDRAM
- 3.4.15 SDRAM refresh
- 3.4.16 Memory-to-CPU prefetch FIFO
- 3.4.17 CPU-to-memory write FIFO
- 3.4.18 SDRAM memory initialization
- 3.5 IBUS Interface
- 3.6 DSU (Deadman’s SW Unit)
- 3.7 Endian Mode Software Issues
- CHAPTER 4 ATM CELL PROCESSOR
- 4.1 Overview
- 4.2 Memory Space
- 4.3 Interruption
- 4.4 Registers for ATM Cell Processing
- 4.4.1 Register map
- 4.4.2 A_GMR (General Mode Register)
- 4.4.3 A_GSR (General Status Register)
- 4.4.4 A_IMR (Interrupt Mask Register)
- 4.4.5 A_RQU (Receiving Queue Underrun Register)
- 4.4.6 A_RQA (Receiving Queue Alert Register)
- 4.4.7 A_VER (Version Register)
- 4.4.8 A_CMR (Command Register)
- 4.4.9 A_CER (Command Extension Register)
- 4.4.10 A_MSA0 to A_MSA3 (Mailbox Start Address Register)
- 4.4.11 A_MBA0 to A_MBA3 (Mailbox Bottom Address Register)
- 4.4.12 A_MTA0 to A_MTA3 (Mailbox Tail Address Register)
- 4.4.13 A_MWA0 to A_MWA3 (Mailbox Write Address Register)
- 4.4.14 A_RCC (Valid Received Cell Counter)
- 4.4.15 A_TCC (Valid Transmitted Cell Counter)
- 4.4.16 A_RUEC (Receive Unprovisioned VPI/VCI Error Cell Counter)
- 4.4.17 A_RIDC (Receive Internal Dropped Cell Counter)
- 4.4.18 A_T1R (T1 Time Register)
- 4.4.19 A_TSR (Time Stamp Register)
- 4.4.20 A_IBBAR (IBUS Base Address Register)
- 4.4.21 A_INBAR (Instruction Base Address Register)
- 4.4.22 A_UMCMD (UTOPIA Management Interface Command Register)
- 4.5 Data Structure
- 4.6 Initialization
- 4.7 Commands
- 4.8 Operations
- CHAPTER 5 ETHERNET CONTROLLER
- 5.1 Overview
- 5.2 Registers
- 5.2.1 Register map
- 5.2.2 En_MACC1 (MAC Configuration Register 1)
- 5.2.3 En_MACC2 (MAC Configuration Register 2)
- 5.2.4 En_IPGT (Back-to-Back IPG Register)
- 5.2.5 En_IPGR (Non Back-to-Back IPG Register)
- 5.2.6 En_CLRT (Collision Register)
- 5.2.7 En_LMAX (Maximum Packet Length Register)
- 5.2.8 En_RETX (Retry Count Register)
- 5.2.9 En_LSA2 (Station Address Register 2)
- 5.2.10 En_LSA1 (Station Address Register 1)
- 5.2.11 En_PTVR (Pause Timer Value Read Register)
- 5.2.12 En_VLTP (VLAN Type Register)
- 5.2.13 En_MIIC (MII Configuration Register)
- 5.2.14 En_MCMD (MII Command Register)
- 5.2.15 En_MADR (MII Address Register)
- 5.2.16 En_MWTD (MII Write Data Register)
- 5.2.17 En_MRDD (MII Read Data Register)
- 5.2.18 En_MIND (MII Indicate Register)
- 5.2.19 En_AFR (Address Filtering Register)
- 5.2.20 En_HT1 (Hash Table Register 1)
- 5.2.21 En_HT2 (Hash Table Register 2)
- 5.2.22 En_CAR1 (Carry Register 1)
- 5.2.23 En_CAR2 (Carry Register 2)
- 5.2.24 En_CAM1 (Carry Register 1 Mask Register)
- 5.2.25 En_CAM2 (Carry Register 2 Mask Register)
- 5.2.26 En_TXCR (Transmit Configuration Register)
- 5.2.27 En_TXFCR (Transmit FIFO Control Register)
- 5.2.28 En_TXDPR (Transmit Descriptor Pointer)
- 5.2.29 En_RXCR (Receive Configuration Register)
- 5.2.30 En_RXFCR (Receive FIFO Control Register)
- 5.2.31 En_RXDPR (Receive Descriptor Pointer)
- 5.2.32 En_RXPDR (Receive Pool Descriptor Pointer)
- 5.2.33 En_CCR (Configuration Register)
- 5.2.34 En_ISR (Interrupt Serves Register)
- 5.2.35 En_MSR (Mask Serves Register)
- 5.3 Operation
- CHAPTER 6 USB CONTROLLER
- 6.1 Overview
- 6.2 Registers
- 6.2.1 Register map
- 6.2.2 U_GMR (USB General Mode Register)
- 6.2.3 U_VER (USB Frame Number/Version Register)
- 6.2.4 U_GSR1 (USB General Status Register 1)
- 6.2.5 U_IMR1 (USB Interrupt Mask Register 1)
- 6.2.6 U_GSR2 (USB General Status Register 2)
- 6.2.7 U_IMR2 (USB Interrupt Mask Register 2)
- 6.2.8 U_EP0CR (USB EP0 Control Register)
- 6.2.9 U_EP1CR (USB EP1 Control Register)
- 6.2.10 U_EP2CR (USB EP2 Control Register)
- 6.2.11 U_EP3CR (USB EP3 Control Register)
- 6.2.12 U_EP4CR (USB EP4 Control Register)
- 6.2.13 U_EP5CR (USB EP5 Control Register)
- 6.2.14 U_EP6CR (USB EP6 Control Register)
- 6.2.15 U_CMR (USB Command Register)
- 6.2.16 U_CA (USB Command Extension Register)
- 6.2.17 U_TEPSR (USB Tx EndPoint Status Register)
- 6.2.18 U_RP0IR (USB Rx Pool0 Information Register)
- 6.2.19 U_RP0AR (USB Rx Pool0 Address Register)
- 6.2.20 U_RP1IR (USB Rx Pool1 Information Register)
- 6.2.21 U_RP1AR (USB Rx Pool1 Address Register)
- 6.2.22 U_RP2IR (USB Rx Pool2 Information Register)
- 6.2.23 U_RP2AR (USB Rx Pool2 Address Register)
- 6.2.24 U_TMSA (USB Tx MailBox Start Address Register)
- 6.2.25 U_TMBA (USB Tx MailBox Bottom Address Register)
- 6.2.26 U_TMRA (USB Tx MailBox Read Address Register)
- 6.2.27 U_TMWA (USB Tx MailBox Write Address Register)
- 6.2.28 U_RMSA (USB Rx MailBox Start Address Register)
- 6.2.29 U_RMBA (USB Rx MailBox Bottom Address Register)
- 6.2.30 U_RMRA (USB Rx MailBox Read Address Register)
- 6.2.31 U_RMWA (USB Rx MailBox Write Address Register)
- 6.3 USB Attachment Sequence
- 6.4 Initialization
- 6.5 Data Transmit Function
- 6.6 Data Receive Function
- 6.6.1 Overview of receive processing
- 6.6.2 Rx Buffer configuration
- 6.6.3 Receive pool settings
- 6.6.4 Data receive mode
- 6.6.5 VR4120A receive processing
- 6.6.6 USB controller receive processing
- 6.6.7 Detection of errors on USB
- 6.6.8 Rx data corruption on Isochronous EndPoint
- 6.6.9 Rx FIFO overrun
- 6.6.10 Rx indication
- 6.7 Power Management
- 6.8 Receiving SOF Packet
- 6.9 Loopback Mode
- 6.10 Example of Connection
- CHAPTER 7 PCI CONTROLLER
- 7.1 Overview
- 7.2 Bus Bridge Functions
- 7.3 PCI Power Management Interface
- 7.4 Functions in Host-mode
- 7.5 Registers
- 7.5.1 Register map
- 7.5.2 P_PLBA (PCI lower base address register)
- 7.5.3 P_IBBA (Internal bus base address register)
- 7.5.4 P_VERR (Version register)
- 7.5.5 P_PCAR (PCI Configuration Address Register)
- 7.5.6 P_PCDR (PCI Configuration Data Register)
- 7.5.7 P_IGSR (Internal bus-side General Status Register)
- 7.5.8 P_IIMR (Internal bus Interrupt Mask Register)
- 7.5.9 P_PGSR (PCI-side General Status Register)
- 7.5.10 P_IIMR (Internal bus Interrupt Mask Register)
- 7.5.11 P_PIMR (PCI Interrupt Mask Register)
- 7.5.12 P_HMCR (Host Mode Control Register)
- 7.5.13 P_PCDR (Power Consumption Data Register)
- 7.5.14 P_PDDR (Power Dissipation Data Register)
- 7.5.15 P_BCNT (Bridge Control Register)
- 7.5.16 P_PPCR (PCI Power Control Register)
- 7.5.17 P_SWRR (Software Reset Register)
- 7.5.18 P_RTMR (Retry Timer Register)
- 7.5.19 P_CONFIG (PCI configuration registers)
- 7.6 Information for Software
- CHAPTER 8 UART
- 8.1 Overview
- 8.2 UART Block Diagram
- 8.3 Registers
- 8.3.1 Register map
- 8.3.2 UARTRBR (UART Receiver data Buffer Register)
- 8.3.3 UARTTHR (UART Transmitter data Holding Register)
- 8.3.4 UARTIER (UART Interrupt Enable Register)
- 8.3.5 UARTDLL (UART Divisor Latch LSB Register)
- 8.3.6 UARTDLM (UART Divisor Latch MSB Register)
- 8.3.7 UARTIIR (UART Interrupt ID Register)
- 8.3.8 UARTFCR (UART FIFO Control Register)
- 8.3.9 UARTLCR (UART Line Control Register)
- 8.3.10 UARTMCR (UART Modem Control Register)
- 8.3.11 UARTLSR (UART Line Status Register)
- 8.3.12 UARTMSR (UART Modem Status Register)
- 8.3.13 UARTSCR (UART Scratch Register)
- CHAPTER 9 TIMER
- CHAPTER 10 MICRO WIRE
- APPENDIX A MIPS III INSTRUCTION SET DETAILS
- APPENDIX B VR4120A COPROCESSOR 0 HAZARDS