NEC Network Controller uPD98502 - Manual (Page 79)

CHAPTER 2 V R 4120A
Preliminary User’s Manual S15543EJ1V0UM 79
There are special symbols used in the instruction formats of Tables 2-17 through 2-21.
REGIMM : Opcode
Sub : Sub-operation code
CO : Sub-operation identifier
BC : BC sub-operation code
br : Branch condition identifier
op : Operation code
Table 2-17. Branch Instructions
Instruction Format and Description
Branch On Equal BEQ rs, rt, offset
If the contents of register rs are equal to that of register rt, the program branches to the target address.
Branch On Not Equal BNE rs, rt, offset
If the contents of register rs are not equal to that of register rt, the program branches to the target
address.
Branch On Less Than
Or Equal To Zero
BLEZ rs, offset
If the contents of register rs are less than or equal to zero, the program branches to the target address.
Branch On Greater
Than Zero
BGTZ rs, offset
If the contents of register rs are greater than zero, the program branches to the target address.
Instruction Format and Description
Branch On Less Than
Zero
BLTZ rs, offset
If the contents of register rs are less than zero, the program branches to the target address.
Branch On Greater
Than Or Equal To Zero
BGEZ rs, offset
If the contents of register rs are greater than or equal to zero, the program branches to the target
address.
Branch On Less Than
Zero And Link
BLTZAL rs, offset
The address of the instruction that follows delay slot is stored to register r31 (link register). If the
contents of register rs are less than zero, the program branches to the target address.
Branch On Greater
Than Or Equal To Zero
And Link
BGEZAL rs, offset
The address of the instruction that follows delay slot is stored to register r31 (link register). If the
contents of register rs are greater than or equal to zero, the program branches to the target address.
Instruction Format and Description
Branch On
Coprocessor 0 True
BC0T offset
Adds the 16-bit offset (shifted left by two bits and sign extended to 32 bits) to the address of the
instruction in the delay slot to calculate the branch target address.
If the conditional signal of the coprocessor 0 is true, the program branches to the target address with
one-instruction delay.
Branch On
Coprocessor 0 False
BC0F offset
Adds the 16-bit offset (shifted left by two bits and sign extended to 32 bits) to the address of the
instruction in the delay slot to calculate the branch target address.
If the conditional signal of the coprocessor 0 is false, the program branches to the target address with
one-instruction delay.
op rs rt offset
REGIMM offset rs sub
COP0 offset BC br