NEC Network Controller uPD98502 - Manual (Page 86)

CHAPTER 2 V R 4120A
86 Preliminary User’s Manual S15543EJ1V0UM
Table 2-22. Operation in Each Stage of Pipeline (MIPS III)
Cycle Phase Mnemonic Description
IF Φ1 IDC Instruction cache address decode
ITLB Instruction address translation
Φ2 ICA Instruction cache array access
ITC Instruction tag check
RF Φ1 IDEC Instruction decode
Φ2 RF Register operand fetch
BAC Branch address calculation
EX
Φ1
EX Execution stage
DVA Data virtual address calculation
SA Store align
Φ2 DCA Data cache address decode/array access
DTLB Data address translation
DC Φ1 DLA Data cache load align
DTC Data tag check
DTD Data transfer to data cache
WB Φ1 DCW Data cache write
WB Write back to register file