NEC Network Controller uPD98502 - Manual (Page 556)

APPENDIX A MIPS III INSTRUCTION SET DETAILS
556 Preliminary User’s Manual S15543EJ1V0UM
SRLV
Shift Right Logical Variable
SRLV
rs
SPECIAL
0 0 0 0 0 0
rt rd
0
0 0 0 0 0
SRLV
0 0 0 1 1 0
31 26 25 21 20 16 15 11 10 6 5 0
6 5 5 5 5 6
Format:
SRLV rd, rt, rs
Description:
The contents of general register rt are shifted right by the number of bits specified by the low-order five bits of
general register rs, inserting zeros into the high-order bits.
The result is placed in register rd.
In 64-bit mode, the operand must be a valid sign-extended, 32-bit value.
Operation:
32 T: s ← GPR [rs]
4...0
GPR [rd] ← 0 s || GPR [rt]
31...s
64 T: s ← GPR [rs]
4...0
temp ← 0 s || GPR [rt]
31...s
GPR [rd] ← (temp
31
)
32
|| temp
Exceptions:
None