6 uartdlm (uart divisor latch msb register) – NEC Network Controller uPD98502 User Manual
Page 417
CHAPTER 8 UART
Preliminary User’s Manual S15543EJ1V0UM
417
8.3.6 UARTDLM (UART Divisor Latch MSB Register)
This register is used to set the divisor (division rate) for the baud rate generator. The data in this register and the
lower 8-bit data in UARTDLL register are together handled as 16-bit data.
Bits
Field
R/W
Default
Description
31:8
Reserved
R/W
0
Hardwired to 0.
7:0
DIVLSB
R/W
-
UART divisor latch (see Table 8-1):
Only accessed when DLAB = 1 in UARTLCR
Table 8-1. Correspondence between Baud Rates and Divisors
Baud Rate
UART Source Clock Frequency
[bps]
18.432 MHz
(Use External Clock)
33.000 MHz
(CPU Clock = 66 MHz)
50.000 MHz
(CPU Clock = 100 MHz)
Divisor
Error
Divisor
Error
Divisor
Error
50
23040 (5A00H)
0
41250 (A122H)
>1 %
62500 (F424H)
0
75
15360 (3C00H)
0
27500 (6B6CH)
>1 %
41667 (A2C3H)
>1 %
110
10473 (28E9H)
0
18750 (493EH)
>1 %
28409 (6EF9H)
>1 %
134.5
8565 (2175H)
0
15335 (3BE7H)
>1 %
23234 (5AC2H)
>1 %
150
7680 (1E00H)
0
13750 (35B6H)
>1 %
20833 (5161H)
>1 %
300
3840 (F00H)
0
6875 (1ADBH)
>1 %
10417 (28B1H)
>1 %
600
1920 (780H)
0
3438 (D6EH)
>1 %
5208 (1458H)
>1 %
1200
920 (398H)
0
1719 (6B7H)
>1 %
2604 (A2CH)
>1 %
1800
640 (280H)
0
1146 (47AH)
>1 %
1736 (6C8H)
>1 %
2000
573 (23DH)
0
1031 (407H)
>1 %
1562 (61AH)
>1 %
2400
480 (1E0H)
0
859 (35BH)
>1 %
1302 (516H)
>1 %
3600
320 (140H)
0
573 (23DH)
>1 %
868 (364H)
>1 %
4800
240 (F0H)
0
430 (1AEH)
>1 %
651 (28BH)
>1 %
7200
160 (A0H)
0
286 (11EH)
>1 %
434 (1B2H)
>1 %
9600
120 (78H)
0
215 (D7H)
>1 %
326 (146H)
>1 %
19200
60 (3CH)
0
107 (6BH)
>1 %
163 (A3H)
>1 %
38400
30 (1EH)
0
54 (36H)
>1 %
81 (51H)
>1 %
56000
21 (15H)
2.04 %
37 (25H)
>1 %
56 (38H)
>1 %
128000
9 (9H)
0
16 (10H)
>1 %
24 (18H)
1.69 %
144000
8 (8H)
0
14 (EH)
2.25 %
22 (16H)
1.38 %
192000
6 (6H)
0
11 (BH)
2.41 %
16 (10H)
1.69 %
230400
5 (5H)
0
9 (9H)
>1 %
14 (EH)
3.22 %
288000
4 (4H)
0
7 (7H)
2.25 %
11 (BH)
1.38 %
384000
3 (3H)
0
5 (5H)
6.90 %
8 (8H)
1.69 %
576000
2 (2H)
0
4 (4H)
11.7 %
5 (5H)
7.83 %
1152000
1 (1H)
0
2 (2H)
11.7 %
3 (3H)
10.6 %
Remark
If UCSEL bit in the S_GMR Register is set, The external UART clock “URCLK” is used as UART source
clock.
If UCSEL bit is reset, 1/2 of CPU clock is used as UART source clock.