NEC Network Controller uPD98502 - Manual (Page 77)

CHAPTER 2 V R 4120A
Preliminary User’s Manual S15543EJ1V0UM 77
Table 2-14. Number of Stall Cycles in Multiply and Divide Instructions
Instruction Number of Instruction Cycles
MULT 1
MULTU 1
DIV 36
DIVU 36
DMULT 3
DMULTU 3
DDIV 68
DDIVU 68
MACC 0
DMACC 0
2.2.2.3 Jump and branch instructions
Jump and branch instructions change the control flow of a program. All jump and branch instructions occur with a
delay of one instruction: that is, the instruction immediately following the jump or branch instruction (this is known as
the instruction in the delay slot) always executes while the target instruction is being fetched from memory.
For instructions involving a link (such as JAL and BLTZAL), the return address is saved in register r31.
Table 2-15. Number of Delay Slot Cycles in Jump and Branch Instructions
Instruction Necessary Number of Cycles
Branch instruction 1
Jump instruction 1
(1) Overview of jump instructions
Subroutine calls in high-level languages are usually implemented with J or JAL instructions, both of which are J-
type instructions. In J-type format, the 26-bit target address shifts left 2 bits and combines with the high-order 4
bits of the current program counter to form a 32-bit or 64-bit absolute address.
Returns, dispatches, and cross-page jumps are usually implemented with the JR or JALR instructions. Both are
R-type instructions that take the 32-bit or 64-bit byte address contained in one of the general registers.
For more information, refer to APPENDIX A MIPS III INSTRUCTION SET DETAILS.
(2) Overview of branch instructions
A branch instruction has a PC-related signed 16-bit offset.
Tables 2-16 through 2-18 show the lists of Jump, Branch, and Expanded ISA instructions, respectively.