NXP Semiconductors CBT3126 - Manual (Page 4)

CBT3126_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 12 October 2009 4 of 13
NXP Semiconductors
CBT3126
Quad FET bus switch
9. Static characteristics
[1] All typical values are measured at V
CC
= 5 V; T
amb
= 25
°
C.
[2] This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
CC
or GND.
[3] Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. ON resistance is
determined by the lowest voltage of the two (A or B) terminals.
10. Dynamic characteristics
[1] This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical ON
resistance of the switch and a load capacitance, when driven by an ideal voltage source (zero output impedance).
[2] t
PLH
and t
PHL
are the same as t
pd
;
t
PZL
and t
PZH
are the same as t
en
;
t
PLZ
and t
PHZ
are the same as t
dis
.
Table 6. Static characteristics
T
amb
=
−
40
°
C to +85
°
C.
Symbol Parameter Conditions Min Typ [1] Max Unit
V
IK
input clamping voltage V
CC
= 4.5 V; I
I
=
−
18 mA - -
−
1.2 V
V
pass
pass voltage V
I
= V
CC
= 5.0 V; I
SW
=
−
100
µ
A - 3.8 - V
I
I
input leakage current V
CC
= 5.5 V; V
I
= GND or 5.5 V - -
±
1
µ
A
I
CC
supply current V
CC
= 5.5 V; I
SW
= 0 mA;
V
I
= V
CC
or GND
- - 3
µ
A
∆
I
CC
additional supply current control pins; per input;
V
CC
= 5.5 V; one input at 3.4 V,
other inputs at V
CC
or GND
[2] - - 2.5 mA
C
I
input capacitance control pins; V
I
= 3 V or 0 V - 1.7 - pF
C
io(off)
off-state input/output capacitance V
O
= 3 V or 0 V; nOE = V
CC
- 3.4 - pF
R
ON
ON resistance V
CC
= 4.0 V [3]
V
I
= 2.4 V; I
I
= 15 mA - 16 22
Ω
V
CC
= 4.5 V
V
I
= 0 V; I
I
= 64 mA - 5 7
Ω
V
I
= 0 V; I
I
= 30 mA - 5 7
Ω
V
I
= 2.4 V; I
I
= 15 mA - 10 15
Ω
Table 7. Dynamic characteristics
T
amb
=
−
40
°
C to +85
°
C; V
CC
= 4.5 V to 5.5 V; for test circuit see Figure 8 .
Symbol Parameter Conditions Min Max Unit
t
pd
propagation delay nA to nB or nB to nA; see Figure 6 [1][2] - 0.25 ns
t
en
enable time nOE to nA or nB; see Figure 7 [2] 1.6 4.5 ns
t
dis
disable time nOE to nA or nB; see Figure 7 [2] 1.0 5.4 ns