Bus master pci interface, Board configuration nvram, Start conditions – National Instruments PCI-1411 User Manual
Page 23: Acquisition window control
Chapter 3
Hardware Overview
3-4
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Bus Master PCI Interface
The PCI/PXI-1411 implements the PCI interface with a National
Instruments custom application-specific integrated circuit (ASIC), the
PCI MITE. The PCI interface can transfer data at a maximum rate of
132 Mbytes/s in bus master mode. The PCI/PXI-1411 can generate 8-, 16-,
and 32-bit memory read and write cycles, both single and multiple. In slave
mode, the PCI/PXI-1411 is a medium-speed decoder that accepts both
memory and configuration cycles. The interface logic ensures that the
PCI/PXI-1411 can meet PCI loading, driving, and timing requirements.
Board Configuration NVRAM
The PCI/PXI-1411 contains onboard nonvolatile RAM (NVRAM) that
configures all registers on power-up.
Start Conditions
The PCI/PXI-1411 can start acquisitions in a variety of conditions:
•
Software control—The PCI/PXI-1411 supports software control of
acquisition start. You can configure the PCI/PXI-1411 to capture a
fixed number of fields or frames. This configuration is useful for
capturing a single frame or a sequence of frames.
•
Trigger control—You can start an acquisition by enabling the external
trigger line. This input can start a video acquisition on a rising or
falling edge.
•
Frame/field selection—With an interlaced camera and the
PCI/PXI-1411 in frame mode, you can program the PCI/PXI-1411
to start an acquisition on any odd or even field.
Acquisition Window Control
You can configure numerous parameters on the PCI/PXI-1411 to control
the video acquisition window. A brief description of each parameter
follows:
•
Acquisition window—The PCI/PXI-1411 allows the user to specify a
particular region of active pixels and active lines within the incoming
video data. The active pixel region selects the starting pixel and
number of pixels to be acquired relative to the assertion edge of the
horizontal (or line) enable signal from the camera. The active line
region selects the starting line and number of lines to be acquired
relative to the assertion edge of the vertical (or frame) enable signal.