4 bypass capacitor recommendations, 5 unused interface power rails, 6 unused power management signals – Nvidia TEGRA DG-04927-001_V01 User Manual
Page 19
Tegra 200 Series Developer Board User Guide
DG-04927-001_v01
Advance Information – Subject to Change
19
NVIDIA CONFIDENTIAL
4.1.4 Bypass Capacitor Recommendations
Table 5 lists the basic recommendations for bypass capacitors near the Tegra 250. In general, one 0.1uf per power pin (or
group for cores) is desirable. These should be placed as close as possible to the respective power pins. In addition, for the
higher power/higher frequency I/O rails one or more 4.7uf bulk capacitor is recommended and should be placed in the general
area of the power and interface pins.
Table 5 Power Supply Capacitor Recommendations for Tegra 250 Supplies
Power Rail
0.1uF Bypass
Capacitors
4.7uF Bulk
Capacitors
Power Rail
0.1uF Bypass
Capacitors
4.7uF Bulk
Capacitors
Cores
VDD_CORE
3
2
VDD_CPU
1
3
VDD_RTC
1
Analog
AVDD_PLLn
1
1 each
AVDD_HDMI
1
AVDD_DSI_CSI
1
AVDD_USB_PLL
1
AVDD_OSC
1
AVDD_USB
1
AVDD_VDAC
1
AVDD_IC_USB
1
1
AVDD_HDMI_PLL
1
AVDD_PEX
1
AVDD_PEX_PLL
1
AVDD_PLLE
1
Digital
VDDIO_DDR
6
VDDIO_DDR_RX
1
VDDIO_NAND
1
1
VDDIO_VI
1
1
VDDIO_HSIC
1
1
VDDIO_SDIO
1
1
VDDIO_BB
1
1
VDDIO_SYS
1
VDDIO_LCD
1
VDDIO_UART
1
VDDIO_AUDIO
1
VDDIO_PEX_CLK
1
VDD_PEX
0
1
Note:
1: AVDD_PLLA_P_C, AVDD_PLLM, AVDD_PLLU, AVDD_PLLX
4.1.5 Unused Interface Power Rails
The example also assumes that all the interfaces are to be used. If a design does not use any functions on one or more of the
interface blocks, the associated power rail does not need to be powered. For the correct handling of each of the rails in this
case, check the Unused Pin section under for the interface in this document. Generally, unused digital power rails can be left
unconnected or tied to ground while unused analog rails should be left unconnected.
4.1.6 Unused Power Management Signals
A few of the signals related to power management may not be required in some designs. This includes SYS_CLK_REQ and
CLK_32K_OUT. If not required, these pins can be configured as GPIOs instead. CORE_PWR_REQ may also not be needed in
all designs, but this pin does not have a GPIO option. If any of these pins are not used, either as their primary function or as a
GPIO (if available), they can be left unconnected.