Nvidia TEGRA DG-04927-001_V01 - Manual (Page 35)

Tegra 200 Series Developer Board User Guide
DG-04927-001_v01 Advance Information – Subject to Change 35
NVIDIA CONFIDENTIAL
4.9 Miscellaneous
4.9.1 Thermal Diode (Temperature Sensor)
Figure 23: Thermal Diode Connection Example
100K
Ω
100K
Ω
10K
Ω
10K
Ω
Table 13. Thermal Diode Pinout
Signal Pin
THERMD_N E6
THERMD_P F7
4.9.2 Debug Interfaces
An optional debug connector providing access to several debugging interfaces can be added to a design, possibly in the early
stages and removed for production. One option is the Debug connector shown in Figure 24. This connector is used with the
E1137 Combo Debug Board. This board interfaces to the Tegra 200 Series Developer Board Debug connector (J10) using a
flex cable. The Combo board provides:
ƒ RS-232 interface on a DB-9 connector which uses UART1 on the Tegra 250
ƒ Standard 20-pin, 0.1” JTAG header
- Can be used with standard ARM software development/debugging hardware
- Provides low level access to the CPUs and AVP
ƒ Ethernet RJ-45 jack by means of a SPI-Ethernet controller (using the Tegra 250 SPI1 interface)
Note that in the circuit in Figure 24, there is an optional resistor on JTAG_TRST_N. For normal JTAG operation, this resistor
should not be present. The JTAG_TRST_N pin on the Tegra 250 selects whether the JTAG interface is to be used for
communicating with the Tegra 250 CPU complex, or for Test/Scan purposes. When JTAG_TRST_N is pulled low, the JTAG
interface is enabled for access to the CPU complex. When high, it is in Test/Scan mode.
When used in the normal operating mode to access the internal CPUs, in order to reset the Tegra 250 JTAG block, a reset
command is used rather than toggling the JTAG_TRST_N pin.