NXP Semiconductors ISP1563 - Manual (Page 11)

NXP Semi
conductor
s
Designing a
Hi-Spe
ed US
B hos
t PCI adapter using
ISP1562/63
AN10050
Applic
atio
n n
o
te
A
N10
050
_ 4
Rev. 04 —
1 No
vember
2007
11 of 1
8
© NX
P
B.
V. 2
007.
A
ll r
igh
ts
r es
er
v ed.
INTA# INTA#
INTA#
3.3 VAUX
RST# RST#
RST# GNT# GNT#
GNT#
PME# PME#
PME#
AD30
AD28
AD26
AD24
IDSEL
IDSEL
IDSEL
AD22
AD20
AD18
AD16
FRAME#
FRAME#
TRDY#
TRDY# TRDY#
STOP# STOP#
STOP#
PAR PAR
PAR
AD15
AD13
AD11
AD9
C/BE0# C/BE0#
C/BE0#
AD6
AD4
AD2
AD0
+5 V
+3.3 V
+
C52
47
μ F / 10 V 47 μ F / 10 V
C48
+
+
C58
47
μ F / 6.3 V
C57
47 μ F / 6.3 V +
C16
0.1
μ F
C53
0.1
μ F
C54
1 nF
C64
100 pF
C15
0.1
μ F
C14
0.1
μ F
C47
1 nF
C46
1 nF
GND
PCICLK
PCICLK PCICLK
REQ# REQ#
REQ#
AD31
AD29
AD27
AD25
C/BE3# C/BE3#
C/BE3#
AD23
AD21
AD19
AD17
C/BE2#
C/BE2#
C/BE2# IRDY#
IRDY# IRDY#
DEVSEL#
DEVSEL#
DEVSEL#
PERR#
PERR# PERR#
SERR# SERR# SERR#
C/BE1#
C/BE1# C/BE1#
AD14
AD12
AD10
AD8
AD7
AD5
AD3
AD1
GND
AD[31:0]
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
CON5
− 12 V
TCK
GND
TDO
+5 V
+5 V
INTB
INTD
PRSNT 1
RESERVED
PRSNT2
TRST
+12 V
TMS
TDI
+5 V
INTA
INTC
+5 V
RESERVED
VIO
RESERVED
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
RESERVED
GND
CLK
GND
REQ
VIO
AD31
AD29
GND
AD27
AD25
3V3
C/BE3
AD23
GND
AD21
AD19
3V3
AD17
C/BE2
GND
IRDY
3V3
DEVSEL
GND
LOCK
PERR
3V3
SERR
3V3
C/BE1
AD14
GND
AD12
AD10
M66EN
A14
A16
A17
A18
A19
A20
A21
A23
A25
A26
A27
A28
A29
A22
A24
A15
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62 A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
3V3_AUX
RST
VIO
GNT
GND
PME
AD30
3V3
AD28
AD26
GND
AD24
IDSEL
3V3
AD22
AD20
GND
AD18
AD16
3V3
FRAME
GND
TRDY
GND
STOP
3V3
RESERVED
RESERVED
GND
PAR
AD15
3V3
AD13
AD11
GND
AD9
AD8
AD7
3V3
AD5
AD3
GND
AD1
VIO
ACK64
+5V
+5V C/BE0
3V3
AD6
AD4
GND
AD2
AD0
VIO
REQ64
+5V
+5V
PCIBUS
Fig 3. ISP1562 eval board schematic – PCI edge connector