NXP Semiconductors ISP1563 - Manual (Page 7)

NXP Semiconductors
AN10050
Designing a Hi-Speed USB host PCI adapter using ISP1562/63
AN10050_4 © NXP B.V. 2007. All rights reserved.
Application note Rev. 04 — 1 November 2007 7 of 18
4. PCB design recommendations
Some important recommendations for a successful PCB design, applicable to both
adapter card and motherboard design solutions, are as follows:
• Typically, a solution using four layers PCB (signal 1, GND, V
CC
, signal 2) is sufficient
for proper routing, allowing you to obtain good functionality and meeting all
compliance tests requirements. Start your design by placing the ISP1562/3 chip, the
major components, and routing of the high-speed DP and DM traces and clock
traces. Also, a complete ‘clean’ solution for routing the power and GND (split planes)
must be defined before you start routing the rest of the signals.
• The trace length for all PCI signals, except the PCI clock signal, to the PCI connector
must be limited to a maximum of 1.5 inches.
• The length of the PCI clock signal from the PCI bus connector to the ISP1562/3 must
be 2.5 inches ± 0.1 inch in length and must be routed to only one load. It must
usually be ‘snaked’. Ensure that all corners of this trace are rounded. Do not use 90
°
sharp corners.
• Route the high-speed USB differential pairs over continuous GND or power planes.
Avoid crossing anti-etch areas and any breaks in the internal planes (plane splits).
The minimum recommended distance to a plane split is 25 mils. You must also avoid
placing a series of via holes near the DP and DM lines because these will create
‘break areas’ in the GND plane below. This is because of the clearance imposed by
the manufacturing process around any via holes to an internal plane.
• Try to keep the length of the DP and DM traces equal. The maximum trace length
mismatch between high-speed USB signal pairs must not be greater than 70 mils.
• Maintain parallelism between USB differential signals, with the trace spacing needed
to achieve 90 Ω differential impedance. To achieve the required impedance of the
pair traces, it is recommended that you use 8 mils traces and keep the distance
between the DP and DM traces at 8 mils. These values may vary, depending on the
actual PCB parameters.
• Avoid corners when routing the differential pairs DP and DM. Any 90° direction
change of traces must be accomplished with two 45 ° turns or by using an arc of an
imaginary circle tangent to the DP and DM lines.
• Avoid routing the USB differential pairs near I/O connectors, signal headers, crystals,
oscillators, magnetic devices and power connectors.
• Maintain the maximum possible distance between high-speed USB differential pairs,
high-speed or low-speed clock, and non-periodic signals. The minimum
recommended distances are as follows:
− 20 mils between the DP and DM traces and low-speed non-periodic signal traces
− 50 mils between the DP and DM traces, and clock or high-speed periodic signal
traces
− 20 mils between two pairs of the DP and DM traces
• Avoid creating stubs to connect the 15 kΩ pull-down resistors or to test points. If a
stub is unavoidable in the design, no stub must be greater than 80 mils.
• Route all the DP and DM lines on one layer. Do not change layers (avoid using vias)
even to avoid crossing a plane split. It is better to place a non-split plane under high-
speed USB signals, ground layer or power layer. It is recommended that you place a
ground layer beneath the DP and DM lines.