Nxp semi conductor s – NXP Semiconductors ISP1563 User Manual
Page 14
NXP Semi
conductor
s
Designing a
Hi-Spe
ed US
B hos
t PCI adapter using
ISP1562/63
AN10050
Applic
atio
n n
o
te
A
N10
050
_
4
Rev. 04 —
1 No
vember
2007
14 of 1
8
© NX
P
B.
V. 2
007.
A
ll r
igh
ts
r
es
er
v
ed.
C17
0.1
μ
F
C48
C19
+3.3 V
C49
Should be placed
as close as
possible to pin 95
Should be placed
as close as
possible to pin 67
C18
0.1
μ
F
1 nF
0.1
μ
F
1 nF
All capacitors should be placed as close as possible
to the corresponding power pins.
+3.3 V
C51
1 nF
C52
1 nF
C53
1 nF
C29
C30
C31
0.1
μ
F
0.1
μ
F
0.1
μ
F
0.1
μ
F
C32
C33
C34
C35
0.1
μ
F
0.1
μ
F
0.1
μ
F
Should be placed as close as
possible to pin 12
C36
0.1
μ
F
SCL
SDA
+3.3 V
C27
0.1
μ
F
1
2
3
4
6
8
5
7
U4A
A1
A3
VCC
NC/WP
SCL
SDA
AT24C01A-2.7
AT24C01A-2.7
A0
A1
A3
VCC
NC/WP
SCL
SDA
U4
1
2
3
4
6
8
7
5
R35
0
Ω
R46
0
Ω
DVAUX
R25
R26
4.7 k
Ω
4.7 k
Ω
R34
0
Ω
DVAUX
R28
51 k
Ω
R33
0
Ω
SEL48M
121
122
123
SCL
SDA
SEL48M
C20
C21
C22
C68
C23
C24
0.1
μ
F
0.1
μ
F
4.7
μ
F
4.7
μ
F
C69
0.1
μ
F
+
0.1
μ
F
0.1
μ
F
+
JP1
HEADER 3
3.3 VAUX
1
2
3
BLM21PG221SN1
C25
C70
C67
0.1
μ
F
470pF
47
μ
F / 6.3 V
D5
LED
R41
330
Ω
+
FB 10
All capacitors should be
placed as close as possible
to the corresponding ferrite
AVAUX
BLM18PG121SN1
FB6
C26
C50
0.1
μ
F
1 nF
C71
+
4.7
μ
F/ 6.3 V
+3.3 V
DVAUX
AVAUX
AD0
AD1
AD2
AD4
AD3
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
AD[0]
AD[1]
AD[2]
AD[3]
AD[4]
AD[5]
AD[6]
AD[7]
AD[8]
AD[9]
AD[10]
AD[11]
AD[12]
AD[13]
AD[14]
AD[15]
AD[16]
AD[17]
AD[18]
AD[19]
AD[20]
AD[21]
AD[22]
AD[23]
AD[24]
AD[25]
AD[26]
AD[27]
AD[28]
AD[29]
AD[30]
AD[31]
AD[31:0]
C/BE0#
C/BE1#
C/BE2#
C/BE3#
C/BE0#
C/BE1#
C/BE2#
C/BE3#
C/BE#[0]
C/BE#[1]
C/BE#[2]
C/BE#[3]
PCICLK
IDSEL
GNT#
AMB1
INTA#
REQ#
FRAME#
TRDY#
IRDY#
DEVSEL#
STOP#
PERR#
SERR#
PAR
PME#
RST#
CLKRUN#
AMB2
AMB3
AMB4
GRN1
GRN2
GRN3
GRN4
OC1_N
OC2_N
OC3_N
OC4_N
PWE1_N
PWE2_N
PWE3_N
PWE4_N
DM1
DM2
DM3
DM4
OC1#
OC2#
OC3#
OC4#
93
91
89
63
DM1
DM2
DM3
DM4
GRN1
GRN2
GRN3
GRN4
AMB1
AMB2
PWE1#
PWE2#
PWE3#
PWE4#
94
92
90
64
97
106
113
115
96
105
112
114
101
108
117
125
DP1
DP2
DP3
DP4
DP1
DP2
DP3
DP4
103
110
119
127
R29
51 k
Ω
R30
51 k
Ω
R36
0
Ω
R37
0
Ω
OC1#
OC2#
OC3#
OC4#
PWE1#
PWE2#
PWE3#
PWE4#
DM1
DM2
DM3
DM4
DP1
DP2
DP3
DP4
RREF
GNDA
IDSEL
GNT#
INTA#
REQ#
FRAME#
TRDY#
IRDY#
DEVSEL#
STOP#
PERR#
SERR#
PAR
PCICLK
PME#
RST#
IDSEL
GNT#
INTA#
REQ#
FRAME#
TRDY#
IRDY#
DEVSEL#
STOP#
PERR#
SERR#
PAR
PCICLK
PME#
RST#
R42
1 k
Ω
72
58
45
33
14
19
18
34
46
47
48
49
51
52
54
55
57
15
17
1
XTAL2
XTAL1
R44
99
98
86
87
12 k
Ω /
1 %
FB7
BLM18PG121SN1
C73
22 pF
C72
22 pF
OSC1
12 MHz
R45
33
Ω
DVAUX
OSC2 48MHz
R38
0
Ω
C74
2.2
μ
F / 10 V
0.1
μ
F
C28
14
8
7
1
IRQ12
IRQ1
IRQ12
IRQ1
A20OUT
KBIRQ1
MUIRQ12
SMI#
A20OUT
KBIRQ1
MUIRQ12
SMI#
3
4
7
8
9
13
SEL2PORTS
5
R27
DVAUX
R31
R32
R39
R40
JP2
HEADER 4 X 2
1
2
3
4
5
7
6
8
DVAUX
4.7 k
Ω
R43
1k
Ω
DVAUX
DVAUX
DVAUX
AVAUX
A
UX1V8
A
UX1V8
REG1V8
REG1V8
REG1V8
V
I(VREG3V3)
V
CC(I/O)
V
CC(I/O)
V
CC(I/O)
V
CC(I/O)
V
CC(I/O)
V
I(V
A
UX3V3)
V
CC(I/O)_A
UX
V
CC(I/O)_A
UX
V
DD
A_A
UX
V
DD
A_A
UX
V
DD
A_A
UX
V
DD
A_A
UX
DVAUX
DVAUX
DVAUX
GND
A
GND
A
GND
A
GND
A
GND
A
GNDD
GNDD
GNDD
GNDD
GNDD
GNDD
GND
A
GND
A
GND
A
GND
A
GND
A
GND
A
GND
A
GND
A
GNDD
11
85
28
53
70
26
21
35
50
67
83
12
6
95
104
111
120
128
2
16
76
88
10
27
56
73
84
100
107
116
124
102
109
118
126
29
42
56
82
81
77
75
74
71
69
68
66
80
79
78
65
62
61
60
44
43
41
40
39
38
37
36
32
31
30
25
24
23
22
20
U3
ISP1563
+
GND
A0
GND
51 k
Ω
51 k
Ω
0
Ω
0
Ω
not to be implemented
FB7 is optional.
Can be directly
tied to ground.
Fig 6. ISP1563 eval board schematic – ISP1563